Advanced-control timers (TIM1/TIM8/TIM20) RM0440
1202/2126 RM0440 Rev 4
28.6.12 TIMx counter (TIMx_CNT)(x = 1, 8, 20)
Address offset: 0x024
Reset value: 0x0000 0000
28.6.13 TIMx prescaler (TIMx_PSC)(x = 1, 8, 20)
Address offset: 0x028
Reset value: 0x0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIF
CPY
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
r
1514131211109876543210
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 UIFCPY: UIF copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in
the TIMxCR1 is reset, bit 31 is reserved and read at 0.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
Non-dithering mode (DITHEN = 0)
The register holds the counter value.
Dithering mode (DITHEN = 1)
The register only holds the non-dithered part in CNT[15:0]. The fractional part is not
available.
1514131211109876543210
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (f
tim_cnt_ck
) is equal to f
tim_psc_ck
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
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