RM0440 Rev 4 1203/2126
RM0440 Advanced-control timers (TIM1/TIM8/TIM20)
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28.6.14 TIMx auto-reload register (TIMx_ARR)(x = 1, 8, 20)
Address offset: 0x02C
Reset value: 0x0000 FFFF
28.6.15 TIMx repetition counter register (TIMx_RCR)(x = 1, 8, 20)
Address offset: 0x030
Reset value: 0x0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ARR[19:16]
rw rw rw rw
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ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 ARR[19:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 28.3.3: Time-base unit on page 1091 for more details about ARR
update and behavior.
The counter is blocked while the auto-reload value is null.
Non-dithering mode (DITHEN = 0)
The register holds the auto-reload value.
Dithering mode (DITHEN = 1)
The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered
part.
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REP[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 REP[15:0]: Repetition counter reload value
This bitfield defines the update rate of the compare registers (i.e. periodic transfers from
preload to active registers) when preload registers are enable. It also defines the update
interrupt generation rate, if this interrupt is enable.
When the repetition down-counter reaches zero, an update event is generated and it
restarts counting from REP value. As the repetition counter is reloaded with REP value only
at the repetition update event UEV, any write to the TIMx_RCR register is not taken in
account until the next repetition update event.
It means in PWM mode (REP+1) corresponds to:
– the number of PWM periods in edge-aligned mode
– the number of half PWM period in center-aligned mode.
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