RM0440 Rev 4 1991/2126
RM0440 FD controller area network (FDCAN)
2008
44.4.17 FDCAN interrupt line select register (FDCAN_ILS)
This register assigns an interrupt generated by a specific group of interrupt flag from the
Interrupt register to one of the two module interrupt lines. For interrupt generation the
respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].
Address offset: 0x0058
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. PERR BERR MISC TFERR SMSG RxFIFO1 RxFIFO0
rw rw rw rw rw rw rw
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 PERR: Protocol error grouping the following interruption
ARAL: Access to reserved address line
PEDL: Protocol error in data phase line
PEAL: Protocol error in arbitration phase line
WDIL: Watchdog interrupt line
BOL: Bus_Off status
EWL: Warning status interrupt line
Bit 5 :BERR: Bit and line error grouping the following interruption
EPL Error passive interrupt line
ELOL: Error logging overflow interrupt line
Bit 4 MISC: Interrupt regrouping the following interruption
TOOL: Timeout occurred interrupt line
MRAFL: Message RAM access failure interrupt line
TSWL: Timestamp wraparound interrupt line
Bit 3 TFERR: Tx FIFO ERROR grouping the following interruption
TEFLL: Tx event FIFO element lost interrupt line
TEFFL: Tx event FIFO full interrupt line
TEFNL: Tx event FIFO new entry interrupt line
TFEL: Tx FIFO empty interrupt line
Bit 2 SMSG: Status message bit grouping the following interruption
TCFL: Transmission cancellation finished interrupt line
TCL: Transmission completed interrupt line
HPML: High-priority message interrupt line
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