FD controller area network (FDCAN) RM0440
1992/2126 RM0440 Rev 4
44.4.18 FDCAN interrupt line enable register (FDCAN_ILE)
Each of the two interrupt lines to the CPU can be enabled/disabled separately by
programming bits EINT0 and EINT1.
Address offset: 0x005C
Reset value: 0x0000 0000
44.4.19 FDCAN global filter configuration register (FDCAN_RXGFC)
Global settings for Message ID filtering. The Global Filter Configuration controls the filter
path for standard and extended messages as described in Figure 669 and Figure 670.
Address offset: 0x0080
Reset value: 0x0000 0000
Bit 1 RxFIFO1: RX FIFO bit grouping the following interruption
RF1LL: Rx FIFO 1 message lost interrupt line
RF1FL: Rx FIFO 1 full Interrupt line
RF1NL: Rx FIFO 1 new message interrupt line
Bit 0 RxFIFO0: RX FIFO bit grouping the following interruption
RF0LL: Rx FIFO 0 message lost interrupt line
RF0FL: Rx FIFO 0 full interrupt line
RF0NL: Rx FIFO 0 new message interrupt line
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EINT1 EINT0
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Bits 31:2 Reserved, must be kept at reset value.
Bit 1 EINT1: Enable interrupt line 1
0: Interrupt line fdcan_intr0_it disabled
1: Interrupt line fdcan_intr0_it enabled
Bit 0 EINT0: Enable interrupt line 0
0: Interrupt line fdcan_intr1_it disabled
1: Interrupt line fdcan_intr1_it enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. LSE[3:0] Res. Res. Res. LSS[4:0]
rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. F0OM F1OM Res. Res. ANFS[1:0] ANFE[1:0] RRFS RRFE
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