RM0440 Rev 4 221/2126
RM0440 Embedded Flash memory (FLASH) for category 2 devices
228
5.7.8 Flash option register (FLASH_OPTR)
Address offset: 0x20
Reset value: 0xFXXX XXXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
Bit 31 ECCD: ECC detection
Set by hardware when two ECC errors have been detected (only if ECCC/ECCD
are previously cleared). When this bit is set, a NMI is generated.
Cleared by writing 1.
Bit 30 ECCC: ECC correction
Set by hardware when one ECC error has been detected and corrected (only if
ECCC/ECCC2/ECCD/ECCD2 are previously cleared). An interrupt is generated
if ECCCIE is set.
Cleared by writing 1.
Bits 29:25 Reserved, must be kept at reset value.
Bit 24 ECCCIE: ECC correction interrupt enable
0: ECCC interrupt disabled
1: ECCC interrupt enabled.
This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR
register is set.
Bit 23 Reserved, must be kept at reset value.
Bit 22 SYSF_ECC: System Flash ECC fail
This bit indicates that the ECC error correction or double ECC error detection is
located in the System Flash.
Bits 21:19 Reserved, must be kept at reset value.
Bits 18:0 ADDR_ECC: ECC fail address
This bit indicates which address in the Flash memory is concerned by the ECC
error correction or by the double ECC error detection.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. IRHEN
NRST_MODE
[1:0]
n
BOOT0
nSW
BOOT0
CCM
SRAM_
RST
SRAM
_PE
nBOOT
1
Res. Res. Res.
WWDG
_SW
IWGD_
STDBY
IWDG_
StOP
IWDG_
SW
rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res.
nRST_
SHDW
nRST_
STDBY
nRST_
STOP
Res. BOR_LEV[2:0] RDP[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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