Peripherals interconnect matrix RM0440
386/2126 RM0440 Rev 4
Triggering signals
The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for
TIM1/TIM8/TIM20) following a configurable timer event.
The input (to slave) is on signals TIMx_ITRx
The input and output signals for TIM1/TIM8/TIM20 are shown in Figure 269: Advanced-
control timer block diagram.
The possible master/slave connections are given in:
• Table 250: TIMx internal trigger connection
Active power mode
Run, Sleep, Low-power run, Low-power sleep.
11.3.2 From timer (TIMx, HRTIM) and EXTI to ADC (ADCx)
Table 65. Interconnect 19
ADC trigger selection
EXTSEL[4:0] or
JEXTSEL[4:0]
ADC triggers signals assignment
ADC1/2 ADC3/4/5
Regular Injected Regular Injected
0 tim1_cc1 tim1_trgo tim3_cc1 tim1_trgo
1 tim1_cc2 tim1_cc4 tim2_cc3 tim1_cc4
2 tim1_cc3 tim2_trgo tim1_cc3 tim2_trgo
3 tim2_cc2 tim2_cc1 tim8_cc1 tim8_cc2
4 tim3_trgo tim3_cc4 tim3_trgo tim4_cc3
5 tim4_cc4 tim4_trgo exti2 tim4_trgo
6 exti11 exti15 tim4_cc1 tim4_cc4
7 tim8_trgo tim8_cc4 tim8_trgo tim8_cc4
8 tim8_trgo2 tim1_trgo2 tim8_trgo2 tim1_trgo2
9 tim1_trgo tim8_trgo tim1_trgo tim8_trgo
10 tim1_trgo2 tim8_trgo2 tim1_trgo2 tim8_trgo2
11 tim2_trgo tim3_cc3 tim2_trgo tim1_cc3
12 tim4_trgo tim3_trgo tim4_trgo tim3_trgo
13 tim6_trgo tim3_cc1 tim6_trgo exti3
14 tim15_trgo tim6_trgo tim15_trgo tim6_trgo
15 tim3_cc4 tim15_trgo tim2_cc1 tim15_trgo
16 tim20_trgo tim20_trgo tim20_trgo tim20_trgo
17 tim20_trgo2 tim20_trgo2 tim20_trgo2 tim20_trgo2
18 tim20_cc1 tim20_cc4 tim20_cc1 tim20_cc2
19 tim20_cc2 hrtim_adc_trg2 hrtim_adc_trg2 hrtim_adc_trg2
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