Direct memory access controller (DMA) RM0440
414/2126 RM0440 Rev 4
Bit 27 TEIF7: transfer error (TE) flag for channel 7
0: no TE event
1: a TE event occurred
Bit 26 HTIF7: half transfer (HT) flag for channel 7
0: no HT event
1: a HT event occurred
Bit 25 TCIF7: transfer complete (TC) flag for channel 7
0: no TC event
1: a TC event occurred
Bit 24 GIF7: global interrupt flag for channel 7
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 23 TEIF6: transfer error (TE) flag for channel 6
0: no TE event
1: a TE event occurred
Bit 22 HTIF6: half transfer (HT) flag for channel 6
0: no HT event
1: a HT event occurred
Bit 21 TCIF6: transfer complete (TC) flag for channel 6
0: no TC event
1: a TC event occurred
Bit 20 GIF6: global interrupt flag for channel 6
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 19 TEIF5: transfer error (TE) flag for channel 5
0: no TE event
1: a TE event occurred
Bit 18 HTIF5: half transfer (HT) flag for channel 5
0: no HT event
1: a HT event occurred
Bit 17 TCIF5: transfer complete (TC) flag for channel 5
0: no TC event
1: a TC event occurred
Bit 16 GIF5: global interrupt flag for channel 5
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 15 TEIF4: transfer error (TE) flag for channel 4
0: no TE event
1: a TE event occurred
Bit 14 HTIF4: half transfer (HT) flag for channel 4
0: no HT event
1: a HT event occurred
Bit 13 TCIF4: transfer complete (TC) flag for channel 4
0: no TC event
1: a TC event occurred
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