RM0440 Rev 4 455/2126
RM0440 Extended interrupts and events controller (EXTI)
460
15.5.6 Pending register 1 (EXTI_PR1)
Address offset: 0x14
Reset value: undefined
15.5.7 Interrupt mask register 2 (EXTI_IMR2)
Address offset: 0x20
Reset value: Direct lines are set to '1', others lines are set to '0'. See Table 98: EXTI lines
connections.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIF31 PIF30 PIF29 Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 Res. PIF17 PIF16
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
1514131211109 8 765432 1 0
PIF15 PIF14 PIF13 PIF12 PIF11 PIF10 PIF9 PIF8 PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:29 PIFx: Pending interrupt flag on line x (x = 31 to 29)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a ‘1’ to the bit.
Bits 28:23 Reserved, must be kept at reset value.
Bits 22:19 PIFx: Pending interrupt flag on line x (x = 22 to 19)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a ‘1’ to the bit.
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 PIFx: Pending interrupt flag on line x (x = 17 to 0)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a ‘1’ to the bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. IM43 IM42 IM41 IM40 Res. Res. IM37 IM36 IM35 IM34 IM33 IM32
rw rw rw rw rw rw rw rw rw rw
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