High-resolution timer (HRTIM) RM0440
996/2126 RM0440 Rev 4
Bit 2 PER: Timer x period
Timer A period event forces the output to its active state.
Note: In up/down mode (UDM bit set to 1), the counter period event is defined as per the
OUTROM[1:0] bit setting.
Bit 1 RESYNC: Timer A resynchronization
Timer A reset event coming solely from software or SYNC input forces the output to its active state.
Note: Other timer reset are not affecting the output when RESYNC=1.
Bit 0 SST: Software set trigger
This bit forces the output to its active state. This bit can only be set by software and is reset by
hardware.
Note: This bit is not preloaded.
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