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STC micro STC8A8K64D4 Series - User Manual
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STC
micro
TM
STC8A8K64D4 series of
Micr
ocontr
ollers
Refer
ence Manual
Date of update
:
2022/3/
1
2
Table of Contents
Main Page
Table of Contents
2
Overview
17
Features, Price and Pins
18
STC8A8K64D4-64Pin/48Pin Family
18
Features and Price(Quasi 16-Bit MCU with 16-Bit Hardware Multiplier and Divider MDU16)
18
Pinouts
21
Pin Descriptions
25
Function Pins Switch
31
Register Related to Function Pin Switch
31
Bus Speed Control Register (BUS_SPEED)
31
Peripheral Port Switch Register 1(P_SW1) (for UART1, CCP, SPI Switching)
31
Clock Selection Register(MCLKOCR)
32
Enhanced PWM Control Register (Pwmncr)
33
LCM Interface Configuration Register (LCMIFCFG)
34
Example Routines
35
USART1 Switch
35
USART2 Switch
36
UART3 Switch
38
UART4 Switch
39
SPI Switch
41
PWM Switch
42
PCA/CCP/PWM Switch
45
I2C Switch
46
Comparator Output Switch
48
Main Clock Output Switch
49
Package Dimensions
52
LQFP44 Package Mechanical Data (12Mm*12Mm)
52
LQFP48 Package Mechanical Data（9Mm*9Mm
53
QFN48 Package Mechanical Data (6Mm*6Mm)
54
LQFP64 Package Mechanical Data（12Mm*12Mm
55
QFN64 Package Mechanical Data（8Mm*8Mm
56
Naming Rules of STC8A8K64D4 Family
56
ISP Download and Typical Application Circuit
58
STC8A8K64D4 Series ISP Download Application Circuit
58
Download Using RS-232 Converter (High Precision ADC), Emulation Supported
58
Download Using RS-232 Converter (General Precision ADC), Emulation Supported
59
Download Using PL2303-GL, Emulation Supported
60
Download Using Universal USB to Serial Tool, Emulation Supported
61
Download Using U8W Tool, Support ISP Online and Offline Download, also Support Emulation
63
Software Simulation USB ISP Download Directly, and Does Not Support Simulation
65
Microcontroller Power Supply Control Reference Circuit
66
Clock, Reset, Power Saving Mode and Power Management
67
System Clock Control
67
System Clock Selection Register (CKSEL)
67
Clock Division Register (CLKDIV)
67
Internal High Speed High Precision IRC Control Register (HIRCCR)
68
External Oscillator Control Register (XOSCCR)
68
Internal 32Khz Low Speed IRC Control Register (IRC32KCR)
68
Main Clock Output Control Register (MCLKOCR)
69
STC8A8K64D4 Series Internal IRC Frequency Adjustment
70
IRC Band Selection Register (IRCBAND)
70
Internal IRC Frequency Adjustment Register (IRTRIM)
70
Internal IRC Frequency Trim Register (LIRTRIM)
70
Clock Divide Register (CLKDIV)
70
Example of Fine-Tuning to Get a User Frequency of 3Mhz
72
System Reset
75
Watch Dog Timer Reset (WDT_CONTR)
75
Software Reset (IAP_CONTR)
76
Low Voltage Reset (RSTCFG)
77
Low Voltage Power-On Reset Reference Circuit (Generally Not Required)
77
Low Voltage Button Reset Reference Circuit
77
Traditional 8051 High Voltage Power-On Reset Reference Circuit
78
External Crystal Oscillator and External Clock Circuit
79
External Crystal Input Circuit
79
External Clock Input Circuit (P1.6 Cannot be Used as General I/O)
79
Clock Stop / Power Saving Mode and System Power Management
79
Power Control Register (PCON)
79
Power-Down Wake-Up Timer
81
Power-Down Wake-Up Timer Count Register (WKTCL,WKTCH)
81
Example Routines
82
System Clock Soure Selection
82
Main Clock Output
84
Application of Watch-Dog Timer
86
User Defined Downloading by Using Software Reset
88
Low Voltage Detection
89
Power Saving Mode
91
Wake up MCU from Power Saving Mode Using INT0/INT1/INT2/INT3/INT4 Interrupts
93
Wake up MCU from Power Saving Mode Using T0/T1/T2/T3/T4 Pin Interrupts
97
Wake up MCU from Power Saving Mode Using Rxd/Rxd2/Rxd3/Rxd4 Pin Interrupts
101
Wake up MCU from Power Saving Mode Using I2C SDA Pin
104
Wake up MCU from Power Saving Mode Using Power-Down Wake-Up Timer
106
Wake up MCU from Power Saving Mode Using LVD Interrupt
108
Power-Down Wake-Up Timer)
108
Wake up MCU from Power Saving Mode Using Comparator Interrupt ( Recommended for Use with Power-Down Wake-Up Timer)
111
Detect the Operating Voltage (Battery Voltage) Using LVD
113
Memory
118
Program Memory
118
Data Memory
118
Internal RAM
119
PSW (Program Status Word Register)
119
On-Chip Extended RAM
120
Auxiliary Register (AUXR)
120
Bus Speed Control Register (BUS_SPEED)
121
Bit Addressable Data Memory in 8051
121
Special Parameters of Memory
123
Unique ID Number and Important Parameter (CHIPID) Stored in Read-Only Special Function Register
125
Interpretation of Global Unique ID Number in CHIP
125
Interpretation of the Internal Reference Signal Source in CHIP
126
Interpretation of Internal 32K IRC Oscillation Frequency in CHIP
126
Interpretation of High Precision IRC Parameters in CHIP
126
Interpretation of Test Time Parameters in CHIP
127
Interpretation of Chip Package Form Number in CHIP
127
Example Routines
128
Read Internal Referrence Voltage Value (Read from CHIPID)
128
Read Internal Referrence Voltage (from Flash)
131
Read Internal Referrence Voltage (Read from RAM)
134
Read the Unique ID (Read from CHIPID)
137
Read the Unique ID (Read from Flash)
140
Read the Unique ID (Read from RAM)
143
Read the Frequency of 32K Power-Down Wake-Up Timer (Read from CHIPID)
146
Read the Frequency of 32K Power-Down Wake-Up Timer (Read from Flash)
150
Read the Frequency of 32K Power-Down Wake-Up Timer (Read from RAM)
153
Read the User-Defined Internal IRC Frequency (Read from CHIPID)
156
Read the User-Defined Internal IRC Frequency (Read from Flash)
162
Read the User-Defined Internal IRC Frequency (Read from RAM)
168
Special Function Registers
170
STC8A8K64D4-64Pin/48Pin Family
170
List of Special Function Registers
172
O Ports
180
Registers Related to I/O
180
Port Data Register (Px)
181
Ports Mode Registers (Pxm0, Pxm1)
181
Pull-Up Resistor Control Registers (Pxpu)
182
Schmitt Trigger Control Registers (Pxncs)
182
Level Shifting Speed Control Registers (Pxsr)
182
Drive Current Control Registers (Pxdr)
182
Port Digital Signal Input Enable Control Register (Pxie)
183
Configure I/O Ports
184
I/O Ports Structure
184
Quasi-Bidirectional I/O (Weak Pull-Up)
184
Push-Pull Output
185
High Impedance Input
185
Open-Drain Output
185
K Pull-Up Resistor
186
How to Set the External Output Speed of the I/O Port
186
How to Set I/O Port Current Drive Capability
187
How to Reduce the External Radiation of I/O Ports
187
Example Routines
188
Port Mode Setting
188
Reading and Writing Operation of Bidirection Port
189
A Typical Circuit Controlled by Triode
192
Typical Control Circuit of LED
192
Interconnection of 3V/5V Devices in Mixed Voltage Power Supply System
192
Make I/O Port Output Low When Power on Reset
193
Circuit Diagram of Driving 8 Digital Leds Using 74HC595
194
Digital Leds Driven Directly by I/O Port Circuit
195
LCD Segment LCD Driven Directly by I/O Port Circuit
195
Instruction Set
215
Interrupt System
218
Interrupt Sources of STC8A8K64D4 Series
218
Structure of STC8A8K64D4 Interrupt
220
Interrupt List of STC8A8K64D4 Series
221
Registers Related to Interrupt
223
Interrupt Enable Registers (Interrupt Enable Bits)
224
Interrupt Request Registers (Interrupt Flags)
228
Interrupt Priority Registers
231
Example Routines
236
INT0 Interrupt (Rising and Falling Edges)
236
INT0 Interrupt (Falling Edge)
237
INT1 Interrupt (Rising and Falling Edges)
239
INT1 Interrupt (Falling Edge)
241
INT2 Interrupt (Falling Edge Only)
243
INT3 Interrupt (Falling Edge Only)
244
INT4 Interrupt (Falling Edge Only)
246
Timer0 Interrupt
248
Timer1 Interrupt
250
Timer2 Interrupt
251
Timer3 Interrupt
253
Timer4 Interrupt
255
UART1 Interrupt
258
UART2 Interrupt
260
UART3 Interrupt
262
UART4 Interrupt
265
LVD Interrupt
267
SPI Interrupt
269
Comparator Interrupt
271
I2C Interrupt
273
O Port Interrupt
276
I/O Port Interrupt Related Registers
276
Port Interrupt Enable Registers (Pxinte)
277
Port Interrupt Flag Registers (Pxintf)
277
Port Interrupt Mode Configuration Registers (Pxim0，Pxim1)
278
Port Interrupt Priority Control Registers (PINIPL, PINIPH)
278
Port Interrupt Power-Down Wake-Up Enable Registers (Pxwkue)
278
Example Routines
280
P0 Falling Edge Interrupt
280
P1 Rising Edge Interrupt
284
P2 Low Level Interrupt
288
Port3 High Level Interrupt
291
Timer/Counter
296
Registers Related to Timers
296
Timer 0/1
297
Timer 0 and 1 Control Register
297
Timer 0/1 Mode Register
297
Timer0 Mode 0 (16-Bit Auto-Reloadable Mode)
298
Timer0 Mode 1 (16-Bit Non-Autoreloadable Mode)
299
Timer 0 Mode 2 (8-Bit Auto-Reloadable Mode)
300
Timer 0 Mode
300
Used as Real-Time Operating System Metronome)
300
Timer 1 Mode 0 (16-Bit Auto-Reloadable Mode)
301
Timer1 Mode 1 (16-Bit Non-Autoreloadable Mode)
302
Timer 1 Mode 2 (8-Bit Auto-Reloadable Mode)
303
Timer 0 Counting Registers
303
Timer 1 Counting Registers
303
Auxiliary Register 1 (AUXR)
304
External Interrupt and Clock Output Control Register (INTCLKO)
304
Timer 0 Calculation Formula
304
Timer 1 Calculation Formula
304
Timer 2 (24-Bit Timer, 8-Bit Prescaler + 16-Bit Timing)
306
Auxiliary Register 1 (AUXR)
306
External Interrupt and Clock Output Control Register (INTCLKO)
306
Timer 2 Counting Registers
306
Timer 2 8-Bit Prescaler Register (TM2PS)
306
Timer 2 Working Mode
306
Timer 2 Calculation Formula
307
Timer 3/4 (24-Bit Timer, 8-Bit Prescaler + 16-Bit Timing)
307
Timer4 and Timer 3 Control Register (T4T3M)
307
Timer 3 Counting Registers
308
Timer 4 Counting Registers
308
Timer 3 8-Bit Prescaler Register (TM3PS)
308
Timer 4 8-Bit Prescaler Register (TM4PS)
309
Timer 3 Working Mode
309
Timer 4 Working Mode
309
Timer 3 Calculation Formula
310
Timer 4 Calculation Formula
310
Example Routines
311
Timer 0 (Mode 0 - 16-Bit Auto Reload)
311
Timer 0 (Mode 1 - 16-Bit Non-Auto Reload)
312
Timer 0 (Mode 2 - 8-Bit Auto Reload)
314
Timer 0 (Mode 3 - 16-Bit Auto Reload with Non-Maskable Interrupt)
316
Timer 0 (External Count - T0 Is Extended for External Falling Edge Interrupt)
318
Timer 0 (Pulse Width Measurement for High-Level Width of INT0)
320
Timer 0 (Mode 0, Divided Clock Output)
322
Timer 1 (Mode 0 - 16-Bit Auto Reload)
324
Timer 1 (Mode 1 - 16-Bit Non-Auto Reload)
326
Timer 1 (Mode 2 - 8-Bit Auto Reload)
328
Timer 1 (External Count - T1 Is Extended for External Falling Edge Interrupt)
330
Timer 1 (Pulse Width Measurement for High-Level Width of INT1)
331
Timer 1 (Mode 0, Divided Clock Output)
334
Timer 1 (Mode 0) Is Used as Baud Rate Generator of UART1
335
Timer 1 (Mode 2) Is Used as Baud Rate Generator of UART1
339
Timer 2 (16-Bit Auto Reload)
343
Timer 2 (External Count - T2 Is Extended for External Falling Edge Interrupt)
345
Timer 2 (Divided Clock Output)
347
Timer 2 Is Used as Baud Rate Generator of UART1
349
Timer 2 Is Used as Baud Rate Generator of UART2
353
Timer 2 Is Used as Baud Rate Generator of UART3
357
Timer 2 Is Used as Baud Rate Generator of UART4
361
Timer 3 (16-Bit Auto Reload)
365
Timer 3 (External Count - T3 Is Extended for External Falling Edge Interrupt)
368
Timer 3 (Divided Clock Output)
370
Timer 3 Is Used as Baud Rate Generator of UART3
372
Timer 4 (16-Bit Auto Reload)
376
Timer 4 (External Count - T4 Is Extended for External Falling Edge Interrupt)
379
Timer 4 (Divided Clock Output)
381
Timer 4 Is Used as Baud Rate Generator of UART4
383
UART Communication
388
UART Function Pin Switch
388
Registers Related to Uarts
388
Uart1
389
UART1 Control Register
389
UART1 Data Register
389
Power Control Register
390
Auxiliary Register 1
390
UART1 Mode 0
390
UART1 Mode 1
391
UART1 Mode 2
393
UART1 Mode 3
394
Automatic Address Recognition
395
UART1 Slave Address Control Registers
395
Uart2
396
UART2 Control Register
396
UART2 Data Register
396
UART2 Mode 0
396
UART2 Mode 1
397
Uart3
399
UART3 Control Register
399
UART3 Data Register
399
UART3 Mode 0
399
UART3 Mode 1
400
Uart4
402
UART4 Control Register
402
UART4 Data Register
402
UART4 Mode 0
402
UART4 Mode 1
403
Precautions of Uarts
405
Example Routines
405
UART1 Using T2 as Baud Rate Generator
405
UART1 Using T1 (Mode 0) as Baud Rate Generator
409
UART1 Using T1 (Mode 2) as Baud Rate Generator
413
UART2 Using T2 as Baud Rate Generator
417
UART3 Using T2 as Baud Rate Generator
421
UART3 Using T3 as Baud Rate Generator
425
UART4 Using T2 as Baud Rate Generator
430
UART4 Using T4 as Baud Rate Generator
434
Serial Multi-Mcus Communication
438
UART to LIN BUS
439
Comparator, Power-Down Detection, Internal Reference Voltage
449
Comparator Output Pin Switching
449
Internal Structure of Comparator
449
Registers Related to Comparator
450
Comparator Control Register 1
450
Comparator Control Register 2
450
Comparator Extended Configuration Register (CMPEXCFG)
451
Example Routines
452
Using Comparator (Interrupt Mode)
452
Using Comparator (Polling Mode)
455
Comparator Is Used for External Power-Down Detection
458
In Time During Power Down)
458
Comparator Is Used to Detect the Operation Voltage (Battery Voltage)
459
Iap/Eeprom/Data-Flash
464
EEPROM Operation Time
464
Registers Related to EEPROM
464
EEPROM Data Register (IAP_DATA)
464
EEPROM Address Registers (IAP_ADDR)
465
EEPROM Command Register (IAP_CMD)
465
EEPROM Trigger Register (IAP_TRIG)
465
EEPROM Control Register (IAP_CONTR)
465
EEPROM Erase Wait Time Control Register (IAP_TPS)
466
EEPROM Size and Address
466
Example Routines
469
EEPROM Basic Operation
469
Read EEPROM Using MOVC
472
Send out the Data in EEPROM Using UART
476
UART1 Reads and Writes EEPROM - Read Using MOVC
480
Password Erasing and Writing - Multi-Sector Backup - UART1 Operation
488
ADC, Internal Reference Voltage
498
Registers Related to ADC
498
ADC Control Register (ADC_CONTR)
498
ADC Configuration Register (ADCCFG)
499
ADC Result Registers (ADC_RES, ADC_RESL)
500
ADC Timing Control Register (ADCTIM)
500
ADC Extended Configuration Registers (ADCEXCFG)
501
ADC Related Calculation Formula
502
ADC Speed Calculation Formula
502
ADC Conversion Result Calculation Formula
502
Reverse Calculation Formula for ADC Input Voltage
502
Reverse Working Voltage Calculation Formula
502
BIT ADC Static Characteristics
502
ADC Application Reference Circuit Diagram
503
High-Precision ADC Reference Circuit Diagram
503
General Precision ADC Reference Circuit Diagram
503
Example Routines
504
ADC Basic Operation (Polling Mode)
504
ADC Basic Operation (Interrupt Mode)
506
Format ADC Conversion Result
509
ADC Converts Multiple Times to Take Average Automatically
511
Detect External Voltage or Battery Voltage Using ADC 15Th Channel
514
Using ADC as Capacitive Sensing Touch Keys
517
Key-Scan Application Circuit Diagram Using ADC
530
Reference Circuit Diagram for Detecting Negative Voltage
531
The Application of Common Addition Circuit in ADC
532
Application of PCA/CCP/PWM
533
PCA Function Pin Switch
533
Registers Related to PCA
533
PCA Control Register (CCON)
534
PCA Mode Register (CMOD)
534
PCA Counter Registers (CL, CH)
534
PCA Mode Control Registers (Ccapmn)
534
PCA Capture Value/Compare Value Registers (Ccapnl, Ccapnh)
535
PCA PWM Mode Control Registers (Pca_Pwmn)
535
PCA Operation Mode
535
Capture Mode
536
Software Timer Mode
536
High Speed Pulse Output Mode
537
Pulse Width Modulation Mode (PWM Mode)
537
Reference Circuit for Implementing 8 ~ 16-Bit DAC Using CCP / PCA Module
541
Example Routines
542
PCA Output PWM (6/7/8/10 Bit)
542
PCA Capture and Measure Pulse Width
545
PCA Implements 16-Bit Software Timing
549
PCA Output High-Speed Pulse
552
PCA Extends External Interrupt
555
Enhanced PWM with 15-Bit Accuracy
559
Enhanced PWM Output Function Pin Switching
559
Registers Related to PWM
560
Enhanced PWM Global Configuration Register (PWMSET)
561
Enhanced PWM Configuration Registers (PWMCFG)
561
PWM Interrupt Flag Register (PWMIF)
562
PWM Fault Detection Control Register (PWMFDCR)
562
PWM Counter Registers (PWMCH, PWMCL)
563
PWM Clock Selection Register (PWMCKS)
563
PWM Trigger ADC Counter Registers (PWMTADC)
563
PWM Level Output Setting Count Value Registers (Pwmnt1，Pwmnt2)
564
PWM Channel Control Registers (Pwmncr)
565
PWM Channel Level Holding Control Registers (Pwmnhld)
565
Example Routines
566
Output Waveforms with Arbitrary Period and Arbitrary Duty
566
PWM Implements Gradient Light (Breathing Light)
572
Use PWM to Trigger ADC Conversion
577
Sysnchronous Serial Peripheral Interface (SPI)
582
SPI Function Pin Switch
582
Registers Related to SPI
582
SPI Status Register (SPSTAT)
582
SPI Control Register (SPCTL)
582
SPI Data Register (SPDAT)
583
SPI Communication Modes
583
Single Master and Single Slave Mode
583
Dual Devices Configuration Mode
584
Single Master and Multiple Slaves Mode
584
Configure SPI
585
Data Format
586
Example Routines
587
Master Routine of Single Master Single Slave Mode (Interrupt Mode)
587
Slave Routine of Single Master Single Slave Mode (Interrupt Mode)
590
Master Routine of Single Master Single Slave Mode (Polling Mode)
592
Slave Routine of Single Master Single Slave Mode (Polling Mode)
594
Routine of Mutual Master-Slave Mode (Interrupt Mode)
596
Routine of Mutual Master-Slave Mode (Polling Mode)
599
C Bus
603
I2C Function Pin Switch
603
Registers Related to I
603
587
603
I 2 C Master Mode
604
I2C Configuration Register (I2CCFG)
604
I 2 C Master Control Register (I2CMSCR)
604
I 2 C Master Auxiliary Control Register (I2CMSAUX)
606
I 2 C Master Status Register (I2CMSST)
606
I 2 C Slave Mode
608
I 2 C Slave Control Register (I2CSLCR)
608
I 2 C Slave Status Register (I2CSLST)
608
I 2 C Slave Address Register (I2CSLADR)
609
I 2 C Data Registers (I2CTXD, I2CRXD)
610
Example Routines
611
C Is Used to Access AT24C256 in Master Mode (Interrupt Mode)
611
I 2 C Is Used to Access AT24C256 in Master Mode AT24C256 (Polling Mode)
617
C Is Used to Access PCF8563 in Master Mode
623
I 2 C Slave Mode (Polling Mode)
628
I 2 C Slave Mode (Polling Mode)
633
Master Codes for Testing I
638
Slave Mode
638
LCM Interface
644
LCM Interface Function Pin Switch
644
Registers Related to LCM
644
LCM Interface Configuration Register (LCMIFCFG)
644
LCM Interface Configuration Register 2 (LCMIFCFG2)
645
LCM Interface Control Register (LCMIFCR)
645
LCM Interface Status Register (LCMIFSTA)
645
LCM Interface Data Registers (LCMIFDATL, LCMIFDATH)
646
LCM Interface Timing Diagram
647
I8080 Mode
647
M6800 Mode
649
Dma
651
Registers Related to DMA
651
Data Read and Write between Memory and Memory (M2M_DMA)
653
M2M_DMA Configuration Register (DMA_M2M_CFG)
653
M2M_DMA Control Register (DMA_M2M_CR)
653
M2M_DMA Status Register (DMA_M2M_STA)
653
M2M_DMA Transfer Total Byte Register (DMA_M2M_AMT)
653
M2M_DMA Transfer Complete Byte Register (DMA_M2M_DONE)
654
M2M_DMA Send Address Registers (Dma_M2M_Txax)
654
M2M_DMA Receive Address Registers (Dma_M2M_Rxax)
654
ADC Automatic Data Storage (ADC_DMA)
655
ADC_DMA Configuration Register (DMA_ADC_CFG)
655
ADC_DMA Control Register (DMA_ADC_CR)
655
ADC_DMA Status Register (DMA_ADC_STA)
655
ADC_DMA Receive Address Registers (Dma_Adc_Rxax)
655
ADC_DMA Configuration Register 2 (DMA_ADC_CFG2)
655
ADC_DMA Channel Enable Registers (Dma_Adc_Chswx)
656
Data Storage Format of ADC_DMA
657
Data Exchange between SPI and Memory (SPI_DMA)
658
SPI_DMA Configuration Register（Dma_Spi_Cfg
658
SPI_DMA Control Register (DMA_SPI_CR)
659
SPI_DMA Status Register (DMA_SPI_STA)
659
SPI_DMA Transfer Total Byte Register (DMA_SPI_AMT)
660
SPI_DMA Transfer Complete Byte Register (DMA_SPI_DONE)
660
SPI_DMA Send Address Registers (Dma_Spi_Txax)
660
SPI_DMA Receive Address Registers (Dma_Spi_Rxax)
660
SPI_DMA Configuration Register 2 (DMA_SPI_CFG2)
660
Data Exchange between UART1 and Memory (UR1T_DMA，UR1R_DMA)
661
UR1T_DMA Configuration Register (DMA_UR1T_CFG)
661
UR1T_DMA Control Register (DMA_UR1T_CR)
661
UR1T_DMA Status Register (DMA_UR1T_STA)
661
UR1T_DMA Transfer Total Byte Register (DMA_UR1T_AMT)
661
UR1T_DMA Transfer Complete Byte Register (DMA_UR1T_DONE)
662
UR1T_DMA Send Address Registers (Dma_Ur1T_Txax)
662
UR1R_DMA Configuration Register (DMA_UR1R_CFG)
662
UR1R_DMA Control Register (DMA_UR1R_CR)
662
UR1R_DMA Status Register (DMA_UR1R_STA)
662
UR1R_DMA Transfer Total Byte Register (DMA_UR1R_AMT)
663
UR1R_DMA Transfer Complete Byte Register (DMA_UR1R_DONE)
663
UR1R_DMA Receive Address Registers (Dma_Ur1T_Rxax)
663
Data Exchange between UART2 and Memory (UR2T_DMA，UR2R_DMA)
664
UR2T_DMA Configuration Register (DMA_UR2T_CFG)
664
UR2T_DMA Control Register (DMA_UR2T_CR)
664
UR2T_DMA Status Register (DMA_UR2T_STA)
664
UR2T_DMA Transfer Total Byte Register (DMA_UR2T_AMT)
664
UR2T_DMA Transfer Complete Byte Register (DMA_UR2T_DONE)
665
UR2T_DMA Send Address Registers (Dma_Ur2T_Txax)
665
UR2R_DMA Configuration Register (DMA_UR2R_CFG)
665
UR2R_DMA Control Register (DMA_UR2R_CR)
665
UR2R_DMA Status Register (DMA_UR2R_STA)
665
UR2R_DMA Transfer Total Byte Register (DMA_UR2R_AMT)
666
UR2R_DMA Transfer Complete Byte Register (DMA_UR2R_DONE)
666
UR2R_DMA Receive Address Registers (Dma_Ur2T_Rxax)
666
Data Exchange between UART3 and Memory (UR3T_DMA，UR3R_DMA)
667
UR3T_DMA Configuration Register (DMA_UR3T_CFG)
667
UR3T_DMA Control Register (DMA_UR3T_CR)
667
UR3T_DMA Status Register (DMA_UR3T_STA)
667
UR3T_DMA Transfer Total Byte Register (DMA_UR3T_AMT)
667
UR3T_DMA Transfer Complete Byte Register (DMA_UR3T_DONE)
668
UR3T_DMA Send Address Registers (Dma_Ur3T_Txax)
668
UR3R_DMA Configuration Register (DMA_UR3R_CFG)
668
UR3R_DMA Control Register (DMA_UR3R_CR)
668
UR3R_DMA Status Register (DMA_UR3R_STA)
668
UR3R_DMA Transfer Total Byte Register (DMA_UR3R_AMT)
669
UR3R_DMA Transfer Complete Byte Register (DMA_UR3R_DONE)
669
UR3R_DMA Receive Address Registers (Dma_Ur3T_Rxax)
669
Data Exchange between UART4 and Memory (UR4T_DMA，UR4R_DMA)
670
UR4T_DMA Configuration Register (DMA_UR4T_CFG)
670
UR4T_DMA Control Register (DMA_UR4T_CR)
670
UR4T_DMA Status Register (DMA_UR4T_STA)
670
UR4T_DMA Transfer Total Byte Register (DMA_UR4T_AMT)
670
UR4T_DMA Transfer Complete Byte Register (DMA_UR4T_DONE)
671
UR4T_DMA Send Address Registers (Dma_Ur4T_Txax)
671
UR4R_DMA Configuration Register (DMA_UR4R_CFG)
671
UR4R_DMA Control Register (DMA_UR4R_CR)
671
UR4R_DMA Status Register (DMA_UR4R_STA)
671
UR4R_DMA Transfer Total Byte Register (DMA_UR4R_AMT)
672
UR4R_DMA Transfer Complete Byte Register (DMA_UR4R_DONE)
672
UR4R_DMA Receive Address Registers (Dma_Ur4T_Rxax)
672
Data Exchange between LCM and Memory (LCM_DMA)
673
LCM_DMA Configuration Register (DMA_LCM_CFG)
673
LCM_DMA Control Register (DMA_LCM_CR)
673
LCM_DMA Status Register (DMA_LCM_STA)
673
LCM_DMA Transfer Total Byte Register (DMA_LCM_AMT)
674
LCM_DMA Transfer Complete Byte Register (DMA_LCM_DONE)
674
LCM_DMA Send Address Registers (Dma_Lcm_Txax)
674
LCM_DMA Receive Address Registers (Dma_Lcm_Rxax)
674
Example Routines
675
UART1 Interrupt Mode and Computer Transceiver Test - DMA Receive Timeout Interrupt
675
UART1 Interrupt Mode and Computer Transceiver Test - DMA Data Check
680
Enhanced Dual Data Pointer
688
Related Special Function Registers
688
1St 16-Bit Data Pointer Registers (DPTR0)
688
2Nd 16-Bit Data Pointer Registers (DPTR1)
688
DPTR Control Register
688
Data Pointer Control Register (TA)
689
Example Routines
690
Example Routine 1
690
Example Routine 2
691
MDU16 Hardware 16-Bit Multiplier and Divider
693
Registers Related to MDU16
693
Operand 1 Data Registers (MD0~MD3)
693
Operand 2 Data Registers (MD4~MD5)
693
MDU Mode Control Register (ARCON)
694
MDU Operation Control Register (OPCON)
694
Netizens' Application of MDU16 (Provide Ideas, for Reference Only)
695
Example Routines
697
Appendix A STC Emulator User Guide
698
Appendix B How to Test I/O Ports
707
Appendix C How to Make the Traditional 8051 MCU EVB Emulatable
708
Appendix D STC-USB Driver Installation Instructions
710
Appendix E Download Step Demo Using USB
773
Appendix F RS485 Automatic Control or I/O Port Control Circuit Diagram
777
Appendix G STC Tool Instruction Manual
778
Overview
778
System Programmable (ISP) Process Description
778
USB Type Online/Offline Download Tool U8W/U8W-Mini
779
Install U8W/U8W-Mini Driver
781
U8W Function Introduction
783
U8W Online Download Instructions
784
U8W Offline Download Instructions
787
U8W-Mini's Function Introduction
795
U8W-Mini Online Download Instructions
796
U8W-Mini Offline Download Instructions
797
Application Circuit Diagram
820
Download Tool
842
Appendix Q Electrical Characteristics
888
Absolute Maximum Rating
888
Appendix R Application Considerations
892
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STC micro STC8A8K64D4 Series Specifications
General
Brand
STC
Model
micro STC8A8K64D4 Series
Category
Microcontrollers
Language
English
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78 pages
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