STC micro STC8A8K64D4 Series - UR2 R_DMA Transfer Total Byte Register (DMA_UR2 R_AMT); UR2 R_DMA Transfer Complete Byte Register (DMA_UR2 R_DONE); UR2 R_DMA Receive Address Registers (Dma_Ur2 T_Rxax)

STC8A8K64D4 Series Manual
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UR2RIF: UR2R_DMA interrupt request flag bit. When UR2R_DMA receives data, the hardware will automatically set
UR2RIF to 1. If the UR2R_DMA interrupt is enabled, it will enter the interrupt service routine. The flag bit needs
to be cleared by software
RXLOSS: UR2R_DMA receive data discard flag. During the UR2R_DMA operation, when the XRAM bus is too busy
to clear the receive FIFO of the UR2R_DMA and the data received by the UR2R_DMA is automatically discarded,
the hardware will automatically set RXLOSS to 1. The flag bit needs to be cleared by software
23.6.10 UR2R_DMA transfer total byte register (DMA_UR2R_AMT)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR2R_AMT
FA4BH
DMA_UR2R_AMT: Set the number of data bytes that need to automatically receive.
Note: The actual number of bytes is (DMA_UR2R_AMT+1), that is, when DMA_UR2R_AMT is set to 0, 1
byte is transferred, and when DMA_UR2R_AMT is set to 255, 256 bytes are transferred.
23.6.11 UR2R_DMA transfer complete byte register
(DMA_UR2R_DONE)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR2R_DONE
FA4CH
DMA_UR2R_DONE: The number of bytes that have been received currently.
23.6.12 UR2R_DMA Receive Address Registers (DMA_UR2T_RXAx)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR2R_RXAH
FA4DH
ADDR[15:8]
DMA_UR2R_RXAL
FA4EH
ADDR[7:0]
DMA_UR2R_RXA: Set the target address for automatically receiving data. Data will be written from this address when
performing a UR2R_DMA operation.