STC micro STC8A8K64D4 Series - Interrupt Request Registers (Interrupt Flags)

STC8A8K64D4 Series Manual
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0: disable DMA_UR3R interrupt
1: enable DMA_UR3R interrupt
UR4TIE: DMA_UR4T (UART 4 send DMA) interrupt enable bit.
0: disable DMA_UR4T interrupt
1: enable DMA_UR4T interrupt
UR4RIE: DMA_UR4R (UART 4 receive DMA) interrupt enable bit.
0: disable DMA_UR4R interrupt
1: enable DMA_UR4R interrupt
LCMIE: DMA_LCM (LCM interface DMA) interrupt enable bit.
0: disable DMA_LCM interrupt
1: enable DMA_LCM interrupt
11.4.2 Interrupt Request Registers (Interrupt flags)
Timer 0 and 1 Control Register
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
TCON
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TF1: Timer/Counter 1 Overflow Flag. Set by hardware on Timer/Counter 1 overflow. It will be automatically cleared by
the hardware when processor enters the Timer 1 interrupt service routine.
TF0: Timer/Counter 0 Overflow Flag. Set by hardware on Timer/Counter 0 overflow. It will be automatically cleared by
the hardware when processor enters the Timer 1 interrupt service routine.
IE1: External Interrupt 1 request flag. It will be automatically cleared when the processor enters the external interrupt 1
service routine.
IE0: External Interrupt 0 request flag. It will be automatically cleared when the processor enters the external interrupt 0
service routine.
Auxiliary Interrupt Flag Register
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
AUXINTIF
EFH
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INT4IF
INT3IF
INT2IF
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T4IF
T3IF
T2IF
INT4IF: external interrupt 4 request flag, which must be cleared by software.
INT3IF: external interrupt 3 request flag, which must be cleared by software.
INT2IF: external interrupt 2 request flag, which must be cleared by software.
T4IF: timer 4 overflow interrupt flag, which must be cleared by software (Note: This bit is a write-only register, not
readable).
T3IF: timer 3 overflow interrupt flag, which must be cleared by software (Note: This bit is a write-only register, not
readable).
T2IF: timer 2 overflow interrupt flag, which must be cleared by software (Note: This bit is a write-only register, not
readable).
Notice:
Ealy 1T 8051 MCU using 0.35um process, STC15 series added a 16-bit reload timer which was the world's first big innovation
of 8051. Due to high manufacturing cost, STC 16-bit reloadable timer 2/3/4 did not design the interrupt request flag registers
for users to access. The interrupt request flag register has only internal hidden flags. The method provided to the user software
to clear the internal hidden flags is: when the user software disables the timer 2/3/4 interrupt, the hardware automatically
clears the internal timer 2/3/4. Hide interrupt request flags.
For product consistency:
The STC8A/ STC8F and subsequent STC8G/STC8H/ STC8C/ STC12H series which adopt 0.18um process add an interrupt
request flag register accessible by the timer 2/3/4 user, but when the timer 2/3/4 interrupt is disabled , the function of the
internal hidden interrupt request flag bit of the hardware automatic clear timer 2/3/4 is still retained. Therefore, do not
arbitrarily disable the timer 2/3/4 interrupt when the timer 2/3/4 does not stop counting, otherwise the hidden interrupt request
flag that actually works will be cleared. It is possible that after the counter overflows again, there is also a case that after the