STC micro STC8A8K64D4 Series - UR2 T_DMA Transfer Complete Byte Register (DMA_UR2 T_DONE); UR2 T_DMA Send Address Registers (Dma_Ur2 T_Txax); UR2 R_DMA Configuration Register (DMA_UR2 R_CFG); UR2 R_DMA Control Register (DMA_UR2 R_CR)

STC8A8K64D4 Series Manual
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23.6.5 UR2T_DMA transfer complete byte register (DMA_UR2T_DONE)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR2T_DONE
FA44H
DMA_UR2T_DONE: The number of bytes that have been sent so far.
23.6.6 UR2T_DMA Send Address Registers (DMA_UR2T_TXAx)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR2T_TXAH
FA45H
ADDR[15:8]
DMA_UR2T_TXAL
FA46H
ADDR[7:0]
DMA_UR2T_TXA: Set the source address of automatic data transmission. Data is read from this address when
performing a UR2T_DMA operation.
23.6.7 UR2R_DMA Configuration Register (DMA_UR2R_CFG)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR2R_CFG
FA48H
UR2RIE
-
-
-
UR2RIP[1:0]
UR2RPTY[1:0]
UR2RIE: UR2R_DMA interrupt enable control bit
0: Disable UR2R_DMA interrupt
1: Enable UR2R_DMA interrupt
UR2RIP[1:0]: UR2R_DMA interrupt priority control bits
UR2RIP[1:0]
Interrupt priority
00
Lowest (0)
01
Lower (1)
10
Higher (2)
11
Highest (3)
UR2RPTY[1:0]：UR2R_DMA Data bus access priority control bits
UR2RPTY [1:0]
Bus access priority
00
Lowest (0)
01
Lower (1)
10
Higher (2)
11
Highest (3)
23.6.8 UR2R_DMA Control Register (DMA_UR2R_CR)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR2R_CR
FA49H
ENUR2R
-
TRIG
-
-
-
-
CLRFIFO
ENUR2R: UR2R_DMA function enable control bit
0: Disable UR2R_DMA function
1: Enable UR2R_DMA function
TRIG: UR2R_DMA UART1 receive trigger control bit
0: Write 0 is invalid
1: Write 1 to start UR2R_DMA receiving data automatically
CLRFIFO: Clear UR2R_DMA receive FIFO control bit
0: Write 0 is invalid
1: Before starting the UR2R_DMA operation, clear the built-in FIFO of the UR2R_DMA firstly
23.6.9 UR2R_DMA Status Register (DMA_UR2R_STA)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR2R_STA
FA4AH
-
-
-
-
-
-
RXLOSS
UR2RIF