STC8A8K64D4 Series Manual
23.5.5 UR1T_DMA transfer complete byte register (DMA_UR1T_DONE)
DMA_UR1T_DONE: The number of bytes that have been sent so far.
23.5.6 UR1T_DMA Send Address Registers (DMA_UR1T_TXAx)
DMA_UR1T_TXA: Set the source address of automatic data transmission. Data is read from this address when
performing a UR1T_DMA operation.
23.5.7 UR1R_DMA Configuration Register (DMA_UR1R_CFG)
UR1RIE: UR1R_DMA interrupt enable control bit
0: Disable UR1R_DMA interrupt
1: Enable UR1R_DMA interrupt
UR1RIP[1:0]: UR1R_DMA interrupt priority control bits
UR1RPTY[1:0]: UR1R_DMA Data bus access priority control bits
23.5.8 UR1R_DMA Control Register (DMA_UR1R_CR)
ENUR1R: UR1R_DMA function enable control bit
0: Disable UR1R_DMA function
1: Enable UR1R_DMA function
TRIG: UR1R_DMA UART1 receive trigger control bit
0: Write 0 is invalid
1: Write 1 to start UR1R_DMA receiving data automatically
CLRFIFO: Clear UR1R_DMA receive FIFO control bit
0: Write 0 is invalid
1: Before starting the UR1R_DMA operation, clear the built-in FIFO of the UR1R_DMA firstly
23.5.9 UR1R_DMA Status Register (DMA_UR1R_STA)
UR1RIF: UR1R_DMA interrupt request flag bit. When UR1R_DMA receives data, the hardware will automatically set
To Next Page
Loading...