TF1: T1 overflow flag. After T1 is enabled to count, it performs adding 1 count from the initial value. TF1 is set by
hardware on T1 overflow and requests interrupt to CPU. It will keep the status until CPU responds the
interrupt and is cleared by hardware automatically. It also can be cleared by software.
TR1: T1 run control bit. It is set or cleared by software to turn the timer on/off. If GATE (TMOD.7) = 0, T1 will start
counting as soon as TR1=1 and stop counting when TR1=0. If GATE (TMOD.7) = 1, T1 is enabled to count
only if TR1 = 1 and INT1 is high.
TF0: T0 overflow flag. After T0 is enabled to count, it performs adding 1 count from the initial value. TF0 is set by
hardware on T0 overflow and requests interrupt to CPU. It will keep the status until CPU responds the
interrupt and is cleared by hardware automatically. It also can be cleared by software.
TR0: T0 run control bit. It is set or cleared by software to turn the timer on/off. If GATE (TMOD.3) = 0, T0 will start
counting as soon as TR0=1 and stop counting when TR0=0. If GATE (TMOD.0) = 1, T0 is enabled to count
only if TR0 = 1 and INT0 is high.
IE1: External Interrupt 1 (INT1/P3.3) request flag. IE1=1 means external interrupt requests interrupt to CPU.It is
cleared by hardware automatically when the CPU responds to the interrupt.
IT1: External Intenupt 1 trigger edge type control bit. If IT1 = 0, INT1 can be triggered by both rising and falling
edges. If IT1 = 1, INT1 can be triggered only by falling edge.
IE0: External Interrupt 0 (INT0/P3.2) request flag. IE0=1 means external interrupt requests interrupt to CPU.It is
cleared by hardware automatically when the CPU responds to the interrupt.
IT0: External Intenupt 0 trigger edge type control bit. If IT0 = 0, INT0 can be triggered by both rising and falling
edges. If IT0 = 1, INT0 can be triggered only by falling edge.
13.2.2 Timer 0/1 Mode Register
T1_GATE: T1 gate control. If GATE/TMOD.7=1, T1 starts only when TR1 is set AND INT1 pin is high.
T0_GATE: T0 gate control. If GATE/TMOD.3 =1, T0 starts only when TR0 is set AND INT0 pin is high.
T1_C/T: T1 mode select bit. If it is reset, T1 is used as a timer (input pulse is from internal system clock). If it is set,
T1 is used as a counter (input pulse is from external T1/P3.5 pin).
T0_C/T: T0 mode select bit. If it is reset, T0 is used as a timer (input pulse is from internal system clock). If it is set,
T0 is used as a counter (input pulse is from external T0/P3.4 pin).
T1_M1/T1_M0: T1 mode select bits.
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