STC micro STC8A8K64D4 Series - UR3 T_DMA Transfer Complete Byte Register (DMA_UR3 T_DONE); UR3 T_DMA Send Address Registers (Dma_Ur3 T_Txax); UR3 R_DMA Configuration Register (DMA_UR3 R_CFG); UR3 R_DMA Control Register (DMA_UR3 R_CR)

STC8A8K64D4 Series Manual
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23.7.5 UR3T_DMA transfer complete byte register (DMA_UR3T_DONE)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR3T_DONE
FA54H
DMA_UR3T_DONE: The number of bytes that have been sent so far.
23.7.6 UR3T_DMA Send Address Registers (DMA_UR3T_TXAx)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR3T_TXAH
FA55H
ADDR[15:8]
DMA_UR3T_TXAL
FA56H
ADDR[7:0]
DMA_UR3T_TXA: Set the source address of automatic data transmission. Data is read from this address when
performing a UR3T_DMA operation.
23.7.7 UR3R_DMA Configuration Register (DMA_UR3R_CFG)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR3R_CFG
FA58H
UR3RIE
-
-
-
UR3RIP[1:0]
UR3RPTY[1:0]
UR3RIE: UR3R_DMA interrupt enable control bit
0: Disable UR3R_DMA interrupt
1: Enable UR3R_DMA interrupt
UR3RIP[1:0]: UR3R_DMA interrupt priority control bits
UR3RIP[1:0]
Interrupt priority
00
Lowest (0)
01
Lower (1)
10
Higher (2)
11
Highest (3)
UR3RPTY[1:0]: UR3R_DMA Data bus access priority control bits
UR3RPTY [1:0]
Bus access priority
00
Lowest (0)
01
Lower (1)
10
Higher (2)
11
Highest (3)
23.7.8 UR3R_DMA Control Register (DMA_UR3R_CR)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR3R_CR
FA59H
ENUR3R
-
TRIG
-
-
-
-
CLRFIFO
ENUR3R: UR3R_DMA function enable control bit
0: Disable UR3R_DMA function
1: Enable UR3R_DMA function
TRIG: UR3R_DMA UART1 receive trigger control bit
0: Write 0 is invalid
1: Write 1 to start UR3R_DMA receiving data automatically
CLRFIFO: Clear UR3R_DMA receive FIFO control bit
0: Write 0 is invalid
1: Before starting the UR3R_DMA operation, clear the built-in FIFO of the UR3R_DMA firstly
23.7.9 UR3R_DMA Status Register (DMA_UR3R_STA)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR3R_STA
FA5AH
-
-
-
-
-
-
RXLOSS
UR3RIF
UR3RIF: UR3R_DMA interrupt request flag bit. When UR3R_DMA receives data, the hardware will automatically set