STC micro STC8A8K64D4 Series - Data Exchange between LCM and Memory (LCM_DMA); LCM_DMA Configuration Register (DMA_LCM_CFG); LCM_DMA Control Register (DMA_LCM_CR); LCM_DMA Status Register (DMA_LCM_STA)

STC8A8K64D4 Series Manual
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23.9 Data exchange between LCM and memory (LCM_DMA)
23.9.1 LCM_DMA Configuration Register (DMA_LCM_CFG)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_LCM_CFG
FA70H
LCMIE
ACT_TX
ACT_RX
-
LCMIP[1:0]
LCMPTY[1:0]
LCMIE: LCM_DMA interrupt enable control bit
0: Disable LCM_DMA interrupt
1: Enable LCM_DMA interrupt
LCMIP [1:0]: LCM_DMA interrupt priority control bits
LCMIP[1:0]
Interrupt priority
00
Lowest (0)
01
Lower (1)
10
Higher (2)
11
Highest (3)
LCMPTY[1:0]: LCM_DMA Data bus access priority control bits
LCMPTY [1:0]
Bus access priority
00
Lowest (0)
01
Lower (1)
10
Higher (2)
11
Highest (3)
23.9.2 LCM_DMA Control Register (DMA_LCM_CR)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_LCM_CR
FA71H
ENLCM
TRIGWC
TRIGWD
TRIGRC
TRIGRD
-
-
CLRFIFO
ENLCM: LCM_DMA function enable control bit
0: Disable LCM_DMA function
1: Enable LCM_DMA function
TRIGWC: LCM_DMA send command mode trigger control bit
0: Write 0 is invalid
1: Write 1 to start LCM_DMA send command mode operation
TRIGWD: LCM_DMA send data mode trigger control bit
0: Write 0 is invalid
1: Write 1 to start LCM_DMA send data mode operation
TRIGRC: LCM_DMA read command mode trigger control bit
0: Write 0 is invalid
1: Write 1 to start LCM_DMA read command mode operation
TRIGRD: LCM_DMA read data mode trigger control bit
0: Write 0 is invalid
1: Write 1 to start LCM_DMA read data mode operation
23.9.3 LCM_DMA Status Register (DMA_LCM_STA)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_LCM_STA
FA72H
-
-
-
-
-
-
TXOVW
LCMIF
LCMIF: LCM_DMA interrupt request flag bit. After the LCM_DMA data exchange is completed, the hardware
automatically sets LCMIF to 1. If the LCM_DMA interrupt is enabled, the interrupt service routine is entered. The
flag bit needs to be cleared by software
TXOVW: LCM_DMA data coverage flag. When LCM_DMA is in the process of data transmission, and LCMIF writes
the LCMIFDATL and LCMIDDATH registers, the data transmission will fail. At this time, the hardware will
automatically set TXOVW to 1. The flag bit needs to be cleared by software