STC micro STC8A8K64D4 Series - I 2 C Master Auxiliary Control Register (I2 CMSAUX); I 2 C Master Status Register (I2 CMSST)

STC8A8K64D4 Series Manual
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SCL
SDA
(output)
0111: Reserved.
1000: Reserved.
1001: Start command + send data command + receive ACK command.
This command is a combination of command 0001, command 0010 and command 0011. After wrting this
command, the controller will execute these three commands in sequence.
1010: Send data command + receive ACK command.
This command is a combination of command 0010 and command 0011. After writing this command, the
controller will execute these two commands in sequence.
1011: Receive data command + send ACK (0) command.
This command is a combination of command 0100 and command 0101. After writing this command, the
controller will execute these two commands in sequence.
Note: The response signal returned by this command is fixed as ACK (0) and is not affected by the
MSACKO bit.
1100: Receive data command + send NAK (1) command.
This command is a combination of command 0100 and command 0101. After writing this command, the
controller will execute these two commands in sequence.
Note: The response signal returned by this command is fixed to NAK (1), and is not affected by the
MSACKO bit.
21.3.3 I
2
C Master Auxiliary Control Register (I2CMSAUX)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
I2CMSAUX
FE88H
-
-
-
-
-
-
-
WDTA
WDTA: I2C data automatic transmission enable bit in master mode.
0: disable automatic transmission
1: enable automatic transmission
If the automatic transmission function is enabled, when the MCU finishes writing to the I2CTXD data register,
the I
2
C controller will trigger the "1010" command automatically, that is, it will send data automatically and
receive the ACK signal.
21.3.4 I
2
C Master Status Register (I2CMSST)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
I2CMSST
FE82H
MSBUSY
MSIF
-
-
-
-
MSACKI
MSACKO
MSBUSY: status bit of I
2
C controller in master mode. (Read-only)
0: the controller is in idle state.
1: the controller is in busy state.
When the I
2
C controller is in master mode, the controller will enter the busy state after sending the START signal in the
idle state. The busy state will be maintained until the STOP signal is successfully transmitted, and the state will
return to the idle.
MSIF: master mode interrupt request bit (interrupt flag bit). When the I
2
C controller in the master mode executes the
MSCMD command in the completion register I2CMSCR, it generates an interrupt signal. This bit is set to 1 by
hardware automatically to request an interrupt to CPU. The MSIF bit must be cleared by software after responding
to the interrupt.
MSACKI: In master mode, it is the ACK datum received after sending the “0011” command to the MSCMD bit in
I2CMSCR.