STC micro STC8A8K64D4 Series

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STC8A8K64D4 Series Manual

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MSACKO: In master mode, it is the ACK signal ready to be transmitted. When the “0101” command is sent to the

MSCMD bit of I2CMSCR, the controller will read the datum of this bit automatically and send it as ACK to SDA.

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Table of Contents2
Overview17
Features, Price and Pins18
STC8A8K64D4-64Pin/48Pin Family18
Features and Price(Quasi 16-Bit MCU with 16-Bit Hardware Multiplier and Divider MDU16)18
Pinouts21
Pin Descriptions25
Function Pins Switch31
Register Related to Function Pin Switch31
Bus Speed Control Register (BUS_SPEED)31
Peripheral Port Switch Register 1(P_SW1) (for UART1, CCP, SPI Switching)31
Clock Selection Register(MCLKOCR)32
Enhanced PWM Control Register (Pwmncr)33
LCM Interface Configuration Register (LCMIFCFG)34
Example Routines35
USART1 Switch35
USART2 Switch36
UART3 Switch38
UART4 Switch39
SPI Switch41
PWM Switch42
PCA/CCP/PWM Switch45
I2C Switch46
Comparator Output Switch48
Main Clock Output Switch49
Package Dimensions52
LQFP44 Package Mechanical Data (12Mm*12Mm)52
LQFP48 Package Mechanical Data（9Mm*9Mm53
QFN48 Package Mechanical Data (6Mm*6Mm)54
LQFP64 Package Mechanical Data（12Mm*12Mm55
QFN64 Package Mechanical Data（8Mm*8Mm56
Naming Rules of STC8A8K64D4 Family56
ISP Download and Typical Application Circuit58
STC8A8K64D4 Series ISP Download Application Circuit58
Download Using RS-232 Converter (High Precision ADC), Emulation Supported58
Download Using RS-232 Converter (General Precision ADC), Emulation Supported59
Download Using PL2303-GL, Emulation Supported60
Download Using Universal USB to Serial Tool, Emulation Supported61
Download Using U8W Tool, Support ISP Online and Offline Download, also Support Emulation63
Software Simulation USB ISP Download Directly, and Does Not Support Simulation65
Microcontroller Power Supply Control Reference Circuit66
Clock, Reset, Power Saving Mode and Power Management67
System Clock Control67
System Clock Selection Register (CKSEL)67
Clock Division Register (CLKDIV)67
Internal High Speed High Precision IRC Control Register (HIRCCR)68
External Oscillator Control Register (XOSCCR)68
Internal 32Khz Low Speed IRC Control Register (IRC32KCR)68
Main Clock Output Control Register (MCLKOCR)69
STC8A8K64D4 Series Internal IRC Frequency Adjustment70
IRC Band Selection Register (IRCBAND)70
Internal IRC Frequency Adjustment Register (IRTRIM)70
Internal IRC Frequency Trim Register (LIRTRIM)70
Clock Divide Register (CLKDIV)70
Example of Fine-Tuning to Get a User Frequency of 3Mhz72
System Reset75
Watch Dog Timer Reset (WDT_CONTR)75
Software Reset (IAP_CONTR)76
Low Voltage Reset (RSTCFG)77
Low Voltage Power-On Reset Reference Circuit (Generally Not Required)77
Low Voltage Button Reset Reference Circuit77
Traditional 8051 High Voltage Power-On Reset Reference Circuit78
External Crystal Oscillator and External Clock Circuit79
External Crystal Input Circuit79
External Clock Input Circuit (P1.6 Cannot be Used as General I/O)79
Clock Stop / Power Saving Mode and System Power Management79
Power Control Register (PCON)79
Power-Down Wake-Up Timer81
Power-Down Wake-Up Timer Count Register (WKTCL,WKTCH)81
Example Routines82
System Clock Soure Selection82
Main Clock Output84
Application of Watch-Dog Timer86
User Defined Downloading by Using Software Reset88
Low Voltage Detection89
Power Saving Mode91
Wake up MCU from Power Saving Mode Using INT0/INT1/INT2/INT3/INT4 Interrupts93
Wake up MCU from Power Saving Mode Using T0/T1/T2/T3/T4 Pin Interrupts97
Wake up MCU from Power Saving Mode Using Rxd/Rxd2/Rxd3/Rxd4 Pin Interrupts101
Wake up MCU from Power Saving Mode Using I2C SDA Pin104
Wake up MCU from Power Saving Mode Using Power-Down Wake-Up Timer106
Wake up MCU from Power Saving Mode Using LVD Interrupt108
Power-Down Wake-Up Timer)108
Wake up MCU from Power Saving Mode Using Comparator Interrupt ( Recommended for Use with Power-Down Wake-Up Timer)111
Detect the Operating Voltage (Battery Voltage) Using LVD113
Memory118
Program Memory118
Data Memory118
Internal RAM119
PSW (Program Status Word Register)119
On-Chip Extended RAM120
Auxiliary Register (AUXR)120
Bus Speed Control Register (BUS_SPEED)121
Bit Addressable Data Memory in 8051121
Special Parameters of Memory123
Unique ID Number and Important Parameter (CHIPID) Stored in Read-Only Special Function Register125
Interpretation of Global Unique ID Number in CHIP125
Interpretation of the Internal Reference Signal Source in CHIP126
Interpretation of Internal 32K IRC Oscillation Frequency in CHIP126
Interpretation of High Precision IRC Parameters in CHIP126
Interpretation of Test Time Parameters in CHIP127
Interpretation of Chip Package Form Number in CHIP127
Example Routines128
Read Internal Referrence Voltage Value (Read from CHIPID)128
Read Internal Referrence Voltage (from Flash)131
Read Internal Referrence Voltage (Read from RAM)134
Read the Unique ID (Read from CHIPID)137
Read the Unique ID (Read from Flash)140
Read the Unique ID (Read from RAM)143
Read the Frequency of 32K Power-Down Wake-Up Timer (Read from CHIPID)146
Read the Frequency of 32K Power-Down Wake-Up Timer (Read from Flash)150
Read the Frequency of 32K Power-Down Wake-Up Timer (Read from RAM)153
Read the User-Defined Internal IRC Frequency (Read from CHIPID)156
Read the User-Defined Internal IRC Frequency (Read from Flash)162
Read the User-Defined Internal IRC Frequency (Read from RAM)168
Special Function Registers170
STC8A8K64D4-64Pin/48Pin Family170
List of Special Function Registers172
O Ports180
Registers Related to I/O180
Port Data Register (Px)181
Ports Mode Registers (Pxm0, Pxm1)181
Pull-Up Resistor Control Registers (Pxpu)182
Schmitt Trigger Control Registers (Pxncs)182
Level Shifting Speed Control Registers (Pxsr)182
Drive Current Control Registers (Pxdr)182
Port Digital Signal Input Enable Control Register (Pxie)183
Configure I/O Ports184
I/O Ports Structure184
Quasi-Bidirectional I/O (Weak Pull-Up)184
Push-Pull Output185
High Impedance Input185
Open-Drain Output185
K Pull-Up Resistor186
How to Set the External Output Speed of the I/O Port186
How to Set I/O Port Current Drive Capability187
How to Reduce the External Radiation of I/O Ports187
Example Routines188
Port Mode Setting188
Reading and Writing Operation of Bidirection Port189
A Typical Circuit Controlled by Triode192
Typical Control Circuit of LED192
Interconnection of 3V/5V Devices in Mixed Voltage Power Supply System192
Make I/O Port Output Low When Power on Reset193
Circuit Diagram of Driving 8 Digital Leds Using 74HC595194
Digital Leds Driven Directly by I/O Port Circuit195
LCD Segment LCD Driven Directly by I/O Port Circuit195
Instruction Set215
Interrupt System218
Interrupt Sources of STC8A8K64D4 Series218
Structure of STC8A8K64D4 Interrupt220
Interrupt List of STC8A8K64D4 Series221
Registers Related to Interrupt223
Interrupt Enable Registers (Interrupt Enable Bits)224
Interrupt Request Registers (Interrupt Flags)228
Interrupt Priority Registers231
Example Routines236
INT0 Interrupt (Rising and Falling Edges)236
INT0 Interrupt (Falling Edge)237
INT1 Interrupt (Rising and Falling Edges)239
INT1 Interrupt (Falling Edge)241
INT2 Interrupt (Falling Edge Only)243
INT3 Interrupt (Falling Edge Only)244
INT4 Interrupt (Falling Edge Only)246
Timer0 Interrupt248
Timer1 Interrupt250
Timer2 Interrupt251
Timer3 Interrupt253
Timer4 Interrupt255
UART1 Interrupt258
UART2 Interrupt260
UART3 Interrupt262
UART4 Interrupt265
LVD Interrupt267
SPI Interrupt269
Comparator Interrupt271
I2C Interrupt273
O Port Interrupt276
I/O Port Interrupt Related Registers276
Port Interrupt Enable Registers (Pxinte)277
Port Interrupt Flag Registers (Pxintf)277
Port Interrupt Mode Configuration Registers (Pxim0，Pxim1)278
Port Interrupt Priority Control Registers (PINIPL, PINIPH)278
Port Interrupt Power-Down Wake-Up Enable Registers (Pxwkue)278
Example Routines280
P0 Falling Edge Interrupt280
P1 Rising Edge Interrupt284
P2 Low Level Interrupt288
Port3 High Level Interrupt291
Timer/Counter296
Registers Related to Timers296
Timer 0/1297
Timer 0 and 1 Control Register297
Timer 0/1 Mode Register297
Timer0 Mode 0 (16-Bit Auto-Reloadable Mode)298
Timer0 Mode 1 (16-Bit Non-Autoreloadable Mode)299
Timer 0 Mode 2 (8-Bit Auto-Reloadable Mode)300
Timer 0 Mode300
Used as Real-Time Operating System Metronome)300
Timer 1 Mode 0 (16-Bit Auto-Reloadable Mode)301
Timer1 Mode 1 (16-Bit Non-Autoreloadable Mode)302
Timer 1 Mode 2 (8-Bit Auto-Reloadable Mode)303
Timer 0 Counting Registers303
Timer 1 Counting Registers303
Auxiliary Register 1 (AUXR)304
External Interrupt and Clock Output Control Register (INTCLKO)304
Timer 0 Calculation Formula304
Timer 1 Calculation Formula304
Timer 2 (24-Bit Timer, 8-Bit Prescaler + 16-Bit Timing)306
Auxiliary Register 1 (AUXR)306
External Interrupt and Clock Output Control Register (INTCLKO)306
Timer 2 Counting Registers306
Timer 2 8-Bit Prescaler Register (TM2PS)306
Timer 2 Working Mode306
Timer 2 Calculation Formula307
Timer 3/4 (24-Bit Timer, 8-Bit Prescaler + 16-Bit Timing)307
Timer4 and Timer 3 Control Register (T4T3M)307
Timer 3 Counting Registers308
Timer 4 Counting Registers308
Timer 3 8-Bit Prescaler Register (TM3PS)308
Timer 4 8-Bit Prescaler Register (TM4PS)309
Timer 3 Working Mode309
Timer 4 Working Mode309
Timer 3 Calculation Formula310
Timer 4 Calculation Formula310
Example Routines311
Timer 0 (Mode 0 - 16-Bit Auto Reload)311
Timer 0 (Mode 1 - 16-Bit Non-Auto Reload)312
Timer 0 (Mode 2 - 8-Bit Auto Reload)314
Timer 0 (Mode 3 - 16-Bit Auto Reload with Non-Maskable Interrupt)316
Timer 0 (External Count - T0 Is Extended for External Falling Edge Interrupt)318
Timer 0 (Pulse Width Measurement for High-Level Width of INT0)320
Timer 0 (Mode 0, Divided Clock Output)322
Timer 1 (Mode 0 - 16-Bit Auto Reload)324
Timer 1 (Mode 1 - 16-Bit Non-Auto Reload)326
Timer 1 (Mode 2 - 8-Bit Auto Reload)328
Timer 1 (External Count - T1 Is Extended for External Falling Edge Interrupt)330
Timer 1 (Pulse Width Measurement for High-Level Width of INT1)331
Timer 1 (Mode 0, Divided Clock Output)334
Timer 1 (Mode 0) Is Used as Baud Rate Generator of UART1335
Timer 1 (Mode 2) Is Used as Baud Rate Generator of UART1339
Timer 2 (16-Bit Auto Reload)343
Timer 2 (External Count - T2 Is Extended for External Falling Edge Interrupt)345
Timer 2 (Divided Clock Output)347
Timer 2 Is Used as Baud Rate Generator of UART1349
Timer 2 Is Used as Baud Rate Generator of UART2353
Timer 2 Is Used as Baud Rate Generator of UART3357
Timer 2 Is Used as Baud Rate Generator of UART4361
Timer 3 (16-Bit Auto Reload)365
Timer 3 (External Count - T3 Is Extended for External Falling Edge Interrupt)368
Timer 3 (Divided Clock Output)370
Timer 3 Is Used as Baud Rate Generator of UART3372
Timer 4 (16-Bit Auto Reload)376
Timer 4 (External Count - T4 Is Extended for External Falling Edge Interrupt)379
Timer 4 (Divided Clock Output)381
Timer 4 Is Used as Baud Rate Generator of UART4383
UART Communication388
UART Function Pin Switch388
Registers Related to Uarts388
Uart1389
UART1 Control Register389
UART1 Data Register389
Power Control Register390
Auxiliary Register 1390
UART1 Mode 0390
UART1 Mode 1391
UART1 Mode 2393
UART1 Mode 3394
Automatic Address Recognition395
UART1 Slave Address Control Registers395
Uart2396
UART2 Control Register396
UART2 Data Register396
UART2 Mode 0396
UART2 Mode 1397
Uart3399
UART3 Control Register399
UART3 Data Register399
UART3 Mode 0399
UART3 Mode 1400
Uart4402
UART4 Control Register402
UART4 Data Register402
UART4 Mode 0402
UART4 Mode 1403
Precautions of Uarts405
Example Routines405
UART1 Using T2 as Baud Rate Generator405
UART1 Using T1 (Mode 0) as Baud Rate Generator409
UART1 Using T1 (Mode 2) as Baud Rate Generator413
UART2 Using T2 as Baud Rate Generator417
UART3 Using T2 as Baud Rate Generator421
UART3 Using T3 as Baud Rate Generator425
UART4 Using T2 as Baud Rate Generator430
UART4 Using T4 as Baud Rate Generator434
Serial Multi-Mcus Communication438
UART to LIN BUS439
Comparator, Power-Down Detection, Internal Reference Voltage449
Comparator Output Pin Switching449
Internal Structure of Comparator449
Registers Related to Comparator450
Comparator Control Register 1450
Comparator Control Register 2450
Comparator Extended Configuration Register (CMPEXCFG)451
Example Routines452
Using Comparator (Interrupt Mode)452
Using Comparator (Polling Mode)455
Comparator Is Used for External Power-Down Detection458
In Time During Power Down)458
Comparator Is Used to Detect the Operation Voltage (Battery Voltage)459
Iap/Eeprom/Data-Flash464
EEPROM Operation Time464
Registers Related to EEPROM464
EEPROM Data Register (IAP_DATA)464
EEPROM Address Registers (IAP_ADDR)465
EEPROM Command Register (IAP_CMD)465
EEPROM Trigger Register (IAP_TRIG)465
EEPROM Control Register (IAP_CONTR)465
EEPROM Erase Wait Time Control Register (IAP_TPS)466
EEPROM Size and Address466
Example Routines469
EEPROM Basic Operation469
Read EEPROM Using MOVC472
Send out the Data in EEPROM Using UART476
UART1 Reads and Writes EEPROM - Read Using MOVC480
Password Erasing and Writing - Multi-Sector Backup - UART1 Operation488
ADC, Internal Reference Voltage498
Registers Related to ADC498
ADC Control Register (ADC_CONTR)498
ADC Configuration Register (ADCCFG)499
ADC Result Registers (ADC_RES, ADC_RESL)500
ADC Timing Control Register (ADCTIM)500
ADC Extended Configuration Registers (ADCEXCFG)501
ADC Related Calculation Formula502
ADC Speed Calculation Formula502
ADC Conversion Result Calculation Formula502
Reverse Calculation Formula for ADC Input Voltage502
Reverse Working Voltage Calculation Formula502
BIT ADC Static Characteristics502
ADC Application Reference Circuit Diagram503
High-Precision ADC Reference Circuit Diagram503
General Precision ADC Reference Circuit Diagram503
Example Routines504
ADC Basic Operation (Polling Mode)504
ADC Basic Operation (Interrupt Mode)506
Format ADC Conversion Result509
ADC Converts Multiple Times to Take Average Automatically511
Detect External Voltage or Battery Voltage Using ADC 15Th Channel514
Using ADC as Capacitive Sensing Touch Keys517
Key-Scan Application Circuit Diagram Using ADC530
Reference Circuit Diagram for Detecting Negative Voltage531
The Application of Common Addition Circuit in ADC532
Application of PCA/CCP/PWM533
PCA Function Pin Switch533
Registers Related to PCA533
PCA Control Register (CCON)534
PCA Mode Register (CMOD)534
PCA Counter Registers (CL, CH)534
PCA Mode Control Registers (Ccapmn)534
PCA Capture Value/Compare Value Registers (Ccapnl, Ccapnh)535
PCA PWM Mode Control Registers (Pca_Pwmn)535
PCA Operation Mode535
Capture Mode536
Software Timer Mode536
High Speed Pulse Output Mode537
Pulse Width Modulation Mode (PWM Mode)537
Reference Circuit for Implementing 8 ~ 16-Bit DAC Using CCP / PCA Module541
Example Routines542
PCA Output PWM (6/7/8/10 Bit)542
PCA Capture and Measure Pulse Width545
PCA Implements 16-Bit Software Timing549
PCA Output High-Speed Pulse552
PCA Extends External Interrupt555
Enhanced PWM with 15-Bit Accuracy559
Enhanced PWM Output Function Pin Switching559
Registers Related to PWM560
Enhanced PWM Global Configuration Register (PWMSET)561
Enhanced PWM Configuration Registers (PWMCFG)561
PWM Interrupt Flag Register (PWMIF)562
PWM Fault Detection Control Register (PWMFDCR)562
PWM Counter Registers (PWMCH, PWMCL)563
PWM Clock Selection Register (PWMCKS)563
PWM Trigger ADC Counter Registers (PWMTADC)563
PWM Level Output Setting Count Value Registers (Pwmnt1，Pwmnt2)564
PWM Channel Control Registers (Pwmncr)565
PWM Channel Level Holding Control Registers (Pwmnhld)565
Example Routines566
Output Waveforms with Arbitrary Period and Arbitrary Duty566
PWM Implements Gradient Light (Breathing Light)572
Use PWM to Trigger ADC Conversion577
Sysnchronous Serial Peripheral Interface (SPI)582
SPI Function Pin Switch582
Registers Related to SPI582
SPI Status Register (SPSTAT)582
SPI Control Register (SPCTL)582
SPI Data Register (SPDAT)583
SPI Communication Modes583
Single Master and Single Slave Mode583
Dual Devices Configuration Mode584
Single Master and Multiple Slaves Mode584
Configure SPI585
Data Format586
Example Routines587
Master Routine of Single Master Single Slave Mode (Interrupt Mode)587
Slave Routine of Single Master Single Slave Mode (Interrupt Mode)590
Master Routine of Single Master Single Slave Mode (Polling Mode)592
Slave Routine of Single Master Single Slave Mode (Polling Mode)594
Routine of Mutual Master-Slave Mode (Interrupt Mode)596
Routine of Mutual Master-Slave Mode (Polling Mode)599
C Bus603
I2C Function Pin Switch603
Registers Related to I603
587603
I 2 C Master Mode604
I2C Configuration Register (I2CCFG)604
I 2 C Master Control Register (I2CMSCR)604
I 2 C Master Auxiliary Control Register (I2CMSAUX)606
I 2 C Master Status Register (I2CMSST)606
I 2 C Slave Mode608
I 2 C Slave Control Register (I2CSLCR)608
I 2 C Slave Status Register (I2CSLST)608
I 2 C Slave Address Register (I2CSLADR)609
I 2 C Data Registers (I2CTXD, I2CRXD)610
Example Routines611
C Is Used to Access AT24C256 in Master Mode (Interrupt Mode)611
I 2 C Is Used to Access AT24C256 in Master Mode AT24C256 (Polling Mode)617
C Is Used to Access PCF8563 in Master Mode623
I 2 C Slave Mode (Polling Mode)628
I 2 C Slave Mode (Polling Mode)633
Master Codes for Testing I638
Slave Mode638
LCM Interface644
LCM Interface Function Pin Switch644
Registers Related to LCM644
LCM Interface Configuration Register (LCMIFCFG)644
LCM Interface Configuration Register 2 (LCMIFCFG2)645
LCM Interface Control Register (LCMIFCR)645
LCM Interface Status Register (LCMIFSTA)645
LCM Interface Data Registers (LCMIFDATL, LCMIFDATH)646
LCM Interface Timing Diagram647
I8080 Mode647
M6800 Mode649
Dma651
Registers Related to DMA651
Data Read and Write between Memory and Memory (M2M_DMA)653
M2M_DMA Configuration Register (DMA_M2M_CFG)653
M2M_DMA Control Register (DMA_M2M_CR)653
M2M_DMA Status Register (DMA_M2M_STA)653
M2M_DMA Transfer Total Byte Register (DMA_M2M_AMT)653
M2M_DMA Transfer Complete Byte Register (DMA_M2M_DONE)654
M2M_DMA Send Address Registers (Dma_M2M_Txax)654
M2M_DMA Receive Address Registers (Dma_M2M_Rxax)654
ADC Automatic Data Storage (ADC_DMA)655
ADC_DMA Configuration Register (DMA_ADC_CFG)655
ADC_DMA Control Register (DMA_ADC_CR)655
ADC_DMA Status Register (DMA_ADC_STA)655
ADC_DMA Receive Address Registers (Dma_Adc_Rxax)655
ADC_DMA Configuration Register 2 (DMA_ADC_CFG2)655
ADC_DMA Channel Enable Registers (Dma_Adc_Chswx)656
Data Storage Format of ADC_DMA657
Data Exchange between SPI and Memory (SPI_DMA)658
SPI_DMA Configuration Register（Dma_Spi_Cfg658
SPI_DMA Control Register (DMA_SPI_CR)659
SPI_DMA Status Register (DMA_SPI_STA)659
SPI_DMA Transfer Total Byte Register (DMA_SPI_AMT)660
SPI_DMA Transfer Complete Byte Register (DMA_SPI_DONE)660
SPI_DMA Send Address Registers (Dma_Spi_Txax)660
SPI_DMA Receive Address Registers (Dma_Spi_Rxax)660
SPI_DMA Configuration Register 2 (DMA_SPI_CFG2)660
Data Exchange between UART1 and Memory (UR1T_DMA，UR1R_DMA)661
UR1T_DMA Configuration Register (DMA_UR1T_CFG)661
UR1T_DMA Control Register (DMA_UR1T_CR)661
UR1T_DMA Status Register (DMA_UR1T_STA)661
UR1T_DMA Transfer Total Byte Register (DMA_UR1T_AMT)661
UR1T_DMA Transfer Complete Byte Register (DMA_UR1T_DONE)662
UR1T_DMA Send Address Registers (Dma_Ur1T_Txax)662
UR1R_DMA Configuration Register (DMA_UR1R_CFG)662
UR1R_DMA Control Register (DMA_UR1R_CR)662
UR1R_DMA Status Register (DMA_UR1R_STA)662
UR1R_DMA Transfer Total Byte Register (DMA_UR1R_AMT)663
UR1R_DMA Transfer Complete Byte Register (DMA_UR1R_DONE)663
UR1R_DMA Receive Address Registers (Dma_Ur1T_Rxax)663
Data Exchange between UART2 and Memory (UR2T_DMA，UR2R_DMA)664
UR2T_DMA Configuration Register (DMA_UR2T_CFG)664
UR2T_DMA Control Register (DMA_UR2T_CR)664
UR2T_DMA Status Register (DMA_UR2T_STA)664
UR2T_DMA Transfer Total Byte Register (DMA_UR2T_AMT)664
UR2T_DMA Transfer Complete Byte Register (DMA_UR2T_DONE)665
UR2T_DMA Send Address Registers (Dma_Ur2T_Txax)665
UR2R_DMA Configuration Register (DMA_UR2R_CFG)665
UR2R_DMA Control Register (DMA_UR2R_CR)665
UR2R_DMA Status Register (DMA_UR2R_STA)665
UR2R_DMA Transfer Total Byte Register (DMA_UR2R_AMT)666
UR2R_DMA Transfer Complete Byte Register (DMA_UR2R_DONE)666
UR2R_DMA Receive Address Registers (Dma_Ur2T_Rxax)666
Data Exchange between UART3 and Memory (UR3T_DMA，UR3R_DMA)667
UR3T_DMA Configuration Register (DMA_UR3T_CFG)667
UR3T_DMA Control Register (DMA_UR3T_CR)667
UR3T_DMA Status Register (DMA_UR3T_STA)667
UR3T_DMA Transfer Total Byte Register (DMA_UR3T_AMT)667
UR3T_DMA Transfer Complete Byte Register (DMA_UR3T_DONE)668
UR3T_DMA Send Address Registers (Dma_Ur3T_Txax)668
UR3R_DMA Configuration Register (DMA_UR3R_CFG)668
UR3R_DMA Control Register (DMA_UR3R_CR)668
UR3R_DMA Status Register (DMA_UR3R_STA)668
UR3R_DMA Transfer Total Byte Register (DMA_UR3R_AMT)669
UR3R_DMA Transfer Complete Byte Register (DMA_UR3R_DONE)669
UR3R_DMA Receive Address Registers (Dma_Ur3T_Rxax)669
Data Exchange between UART4 and Memory (UR4T_DMA，UR4R_DMA)670
UR4T_DMA Configuration Register (DMA_UR4T_CFG)670
UR4T_DMA Control Register (DMA_UR4T_CR)670
UR4T_DMA Status Register (DMA_UR4T_STA)670
UR4T_DMA Transfer Total Byte Register (DMA_UR4T_AMT)670
UR4T_DMA Transfer Complete Byte Register (DMA_UR4T_DONE)671
UR4T_DMA Send Address Registers (Dma_Ur4T_Txax)671
UR4R_DMA Configuration Register (DMA_UR4R_CFG)671
UR4R_DMA Control Register (DMA_UR4R_CR)671
UR4R_DMA Status Register (DMA_UR4R_STA)671
UR4R_DMA Transfer Total Byte Register (DMA_UR4R_AMT)672
UR4R_DMA Transfer Complete Byte Register (DMA_UR4R_DONE)672
UR4R_DMA Receive Address Registers (Dma_Ur4T_Rxax)672
Data Exchange between LCM and Memory (LCM_DMA)673
LCM_DMA Configuration Register (DMA_LCM_CFG)673
LCM_DMA Control Register (DMA_LCM_CR)673
LCM_DMA Status Register (DMA_LCM_STA)673
LCM_DMA Transfer Total Byte Register (DMA_LCM_AMT)674
LCM_DMA Transfer Complete Byte Register (DMA_LCM_DONE)674
LCM_DMA Send Address Registers (Dma_Lcm_Txax)674
LCM_DMA Receive Address Registers (Dma_Lcm_Rxax)674
Example Routines675
UART1 Interrupt Mode and Computer Transceiver Test - DMA Receive Timeout Interrupt675
UART1 Interrupt Mode and Computer Transceiver Test - DMA Data Check680
Enhanced Dual Data Pointer688
Related Special Function Registers688
1St 16-Bit Data Pointer Registers (DPTR0)688
2Nd 16-Bit Data Pointer Registers (DPTR1)688
DPTR Control Register688
Data Pointer Control Register (TA)689
Example Routines690
Example Routine 1690
Example Routine 2691
MDU16 Hardware 16-Bit Multiplier and Divider693
Registers Related to MDU16693
Operand 1 Data Registers (MD0~MD3)693
Operand 2 Data Registers (MD4~MD5)693
MDU Mode Control Register (ARCON)694
MDU Operation Control Register (OPCON)694
Netizens' Application of MDU16 (Provide Ideas, for Reference Only)695
Example Routines697
Appendix A STC Emulator User Guide698
Appendix B How to Test I/O Ports707
Appendix C How to Make the Traditional 8051 MCU EVB Emulatable708
Appendix D STC-USB Driver Installation Instructions710
Appendix E Download Step Demo Using USB773
Appendix F RS485 Automatic Control or I/O Port Control Circuit Diagram777
Appendix G STC Tool Instruction Manual778
Overview778
System Programmable (ISP) Process Description778
USB Type Online/Offline Download Tool U8W/U8W-Mini779
Install U8W/U8W-Mini Driver781
U8W Function Introduction783
U8W Online Download Instructions784
U8W Offline Download Instructions787
U8W-Mini's Function Introduction795
U8W-Mini Online Download Instructions796
U8W-Mini Offline Download Instructions797
Application Circuit Diagram820
Download Tool842
Appendix Q Electrical Characteristics888
Absolute Maximum Rating888
Appendix R Application Considerations892

STC micro STC8A8K64D4 Series - Page 607

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