STC micro STC8A8K64D4 Series - LCM Interface Configuration Register 2 (LCMIFCFG2); LCM Interface Control Register (LCMIFCR); LCM Interface Status Register (LCMIFSTA)

STC8A8K64D4 Series Manual
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00
Lowest (0)
01
Lower (1)
10
Higher (2)
11
Highest (3)
LCMIFDPS[1:0]: LCM interface data pin selection bit
LCMIFDPS [1:0]
D16_D8
High byte DAT[15:8]
Low byte DAT[7:0]
00
0
N/A
P2[7:0]
01
0
N/A
P6[7:0]
10
0
N/A
P2[7:0]
11
0
N/A
P6[7:0]
00
1
P2[7:0]
P0[7:0]
01
1
P6[7:0]
P2[7:0]
10
1
P2[7:0]
P7[7:0]
11
1
P6[7:0]
P7[7:0]
D16_D8: LCM interface data width control bit
0: 8-bit data width
1: 16-bit data width
M68_I80: LCM interface mode selection bit
0: I8080 mode
1: M6800 mode
22.2.2 LCM Interface Configuration Register 2 (LCMIFCFG2)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
LCMIFCFG2
FE51H
-
LCMIFCPS[1:0]
SETUPT[2:0]
HOLDT[1:0]
LCMIFCPS[1:0]: LCM interface control pin selection bit
LCMIFCPS [1:0]
RS
RD signal of I8080
E signal of M6800
WR signal of I8080
RW signal of M6800
00
P4.1
P4.4
P4.3
01
P4.1
P3.7
P3.6
10
P4.1
P4.2
P4.0
11
P4.0
P3.7
P3.6
SETUPT[2:0]: Data setup time control bit for LCM interface communication (see timing diagrams in subsequent
chapters for details)
HOLDT[1:0]: Data hold time control bit for LCM interface communication (see the timing diagram in the subsequent
chapters for details)
22.2.3 LCM Interface Control Register (LCMIFCR)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
LCMIFCR
FE52H
ENLCMIF
-
-
-
-
CMD[2:0]
ELCMIF: LCM interface enable control bit
0: Disable LCM interface function
1: Enable LCM interface function
CMD[2:0]: LCM interface trigger command
CMD[2:0]
trigger command
100
Write command
101
Write data
110
Read command/status
111
Read data
22.2.4 LCM Interface Status Register (LCMIFSTA)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0