STC micro STC8A8K64D4 Series - Data Exchange between SPI and Memory (SPI_DMA); SPI_DMA Configuration Register（Dma_Spi_Cfg

STC8A8K64D4 Series Manual
- 642 -
The form is as follows:
ADC
channel
Offset address
Data
1
st
channel
0
high byte of the 1st ADC conversion result of the 1st enabled channel
1
low byte of the 1st ADC conversion result of the 1st enabled channel
2
high byte of the 2nd ADC conversion result of the 1st enabled channel
3
low byte of the 2nd ADC conversion result of the 1st enabled channel
...
...
2n-2
high byte of the nth ADC conversion result of the 1st enabled channel
2n-1
low byte of the nth ADC conversion result of the 1st enabled channel
2n
ADC channel number of 1st channel
2n+1
remainder after the average value of the n ADC conversion results of the 1st
channel
2n+2
high byte of the average value of the n ADC conversion results of the 1st
channel
2n+3
low byte of the average value of the n ADC conversion results of the 1st channel
2
nd
channel
(2n+3) + 0
high byte of the 1st ADC conversion result of the 2nd enabled channel
(2n+3) + 1
low byte of the 1st ADC conversion result of the 2nd enabled channel
(2n+3) + 2
high byte of the 2nd ADC conversion result of the 2nd enabled channel
(2n+3) + 3
low byte of the 2nd ADC conversion result of the 2nd enabled channel
...
...
(2n+3) + 2n-2
high byte of the nth ADC conversion result of the enabled 2nd channel
(2n+3) + 2n-1
low byte of the nth ADC conversion result of the enabled 2nd channel
(2n+3) + 2n
ADC channel number of 2nd channel
(2n+3) + 2n+1
remainder after the average value of the n ADC conversion results of 2nd
channel
(2n+3) + 2n+2
high byte of the average value of n ADC conversion results of 2nd channel
(2n+3) + 2n+3
low byte of the average value of n ADC conversion results of 2nd channel
...
...
mth
channel
(m-1)(2n+3) + 0
high byte of the 1st ADC conversion result of the enabled mth channel
(m-1)(2n+3) + 1
low byte of the 1st ADC conversion result of the enabled mth channel
(m-1)(2n+3) + 2
high byte of the 2nd ADC conversion result of the enabled mth channel
(m-1)(2n+3) + 3
low byte of the 2nd ADC conversion result of the enabled mth channel
...
...
(m-1)(2n+3) + 2n-2
high byte of the nth ADC conversion result of the enabled mth channel
(m-1)(2n+3) + 2n-1
low byte of the nth ADC conversion result of the enabled mth channel
(m-1)(2n+3) + 2n
ADC channel number of the mth channel
(m-1)(2n+3) + 2n+1
remainder after the average value of the n ADC conversion results of the mth
channel
(m-1)(2n+3) + 2n+2
high byte of the average value of the n ADC conversion results of the mth
channel
(m-1)(2n+3) + 2n+3
low byte of the average value of the n ADC conversion results of the mth
channel
23.4 Data exchange between SPI and memory (SPI_DMA)
23.4.1 SPI_DMA Configuration Register（DMA_SPI_CFG）
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_SPI_CFG
FA20H
SPIIE
ACT_TX
ACT_RX
-
SPIIP[1:0]
SPIPTY[1:0]
SPIIE: SPI_DMA interrupt enable control bit
0: Disable SPI_DMA interrupt
1: Enable SPI_DMA interrupt
ACT_TX: SPI_DMA transmit data control bit