STC8A8K64D4 Series Manual
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ELVD BIT IE.6
LVDF EQU 20H ;PCON.5
P0M1 DATA 093H
P0M0 DATA 094H
P1M1 DATA 091H
P1M0 DATA 092H
P2M1 DATA 095H
P2M0 DATA 096H
P3M1 DATA 0B1H
P3M0 DATA 0B2H
P4M1 DATA 0B3H
P4M0 DATA 0B4H
P5M1 DATA 0C9H
P5M0 DATA 0CAH
ORG 0000H
LJMP MAIN
ORG 0033H
LJMP LVDISR
ORG 0100H
LVDISR:
ANL PCON,#NOT LVDF ;Clear interrupt flag
CPL P3.2 ;Test port
RETI
MAIN:
MOV SP, #5FH
MOV P0M0, #00H
MOV P0M1, #00H
MOV P1M0, #00H
MOV P1M1, #00H
MOV P2M0, #00H
MOV P2M1, #00H
MOV P3M0, #00H
MOV P3M1, #00H
MOV P4M0, #00H
MOV P4M1, #00H
MOV P5M0, #00H
MOV P5M1, #00H
ANL PCON,#NOT LVDF ;LVDF flag needs to be cleared after power on
; MOV RSTCFG,#ENLVR | LVD3V0 ;Low voltage reset when 3.0V is enabled, no LVD interrupt is generated
MOV RSTCFG,#LVD3V0 ;Low voltage interrupt when 3.0V is enabled
SETB ELVD ;Enable LVD interrupt
SETB EA
JMP $
END
6.7.6 Power Saving Mode
C language code
// Operating frequency for test is 11.0592MHz
#include "reg51.h"
#include "intrins.h"
#define IDL 0x01 //PCON.0