DORD: Set the transmitted or received SPI data order.
0: The MSB of the data is transmitted firstly.
1: The LSB of the data is transmitted firstly.
MSTR: Master/Slave mode select bit.
To set the mastert mode:
If SSIG = 0, the SS pin must be high and set MSTR to 1.
If SSIG = 1, it only needs to set MSTR to 1 (ignoring the SS pin level).
To set the slave mode:
If SSIG = 0, the SS pin must be low (regardless of the MSTR bit).
If SSIG = 1, it only needs to set MSTR to 0 (ignoring the SS pin level).
CPOL: SPI clock polarity select bit.
0：SCLK is low when idle. The leading edge of SCLK is the rising edge and the trailing edge is the falling edge.
1：SCLK is high when idle. The leading edge of SCLK is the falling edge and the trailing edge is the rising edge.
CPHA: SPI clock phase select bit.
0: The first bit of datum is driven when SS pin is low. The datum changes on the trailing edge of SCLK and is
sampled on the leading edge of SCLK. (SSIG must be 0.)
1: The datum is driven on the leading edge of SCLK, and is sampled on the trailing edge.
SPR[1:0]: SPI clock frequency select bits
The SPDAT holds the data to be transmitted or the data received.
20.3 SPI Communication Modes
There are three SPI communication modes: single master and single slave mode, dual devices configuration mode
(any one of them can be a master or slave), single master and multiple slaves mode.
20.3.1 Single Master and Single Slave Mode
Two devices are connected, one of which is fixed as a master and the other as a slave.
Master settings: SSIG set to 1, MSTR set to 1, fixed to be master mode. The master can use any port to connect
the slave SS pin, pull down the slave SS pin to enable the slave.
Slave settings: SSIG is set to 0, SS pin as the chip select signal of the slave.
Single master single slave connection configuration diagram is shown as follows:
To Next Page
Loading...