STC micro STC8A8K64D4 Series - Software Reset (IAP_CONTR)

STC8A8K64D4 Series Manual
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CLR_WDT: WDT clear bit.
0: No operation
1: WDT is cleared. This bit will be cleared by hardware automatically.
IDL_WDT: WDT control bit in IDLE mode.
0: WDT is disabled in IDLE mode.
1: WDT is enabled in IDLE mode, and the WDT will continue counting.
WDT_PS[2:0]: Watchdog timer clock division factor
WDT_PS[2:0]
division factor
Overflow time @12MHz
Overflow time @20MHz
000
2
 65.5 ms
 39.3 ms
001
4
 131 ms
 78.6 ms
010
8
 262 ms
 157 ms
011
16
 524 ms
 315 ms
100
32
 1.05 s
 629 ms
101
64
 2.10 s
 1.26 s
110
128
 4.20 s
 2.52 s
111
256
 8.39 s
 5.03 s
The WDT overflow time is determined by the following equation:
WDT overflow time =
12 × 32768 × 2
(WDT_PS+1)
SYSclk
(s)
6.3.2 Software reset (IAP_CONTR)
IAP_CONTR (IAP Control Register)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
IAP_CONTR
C7H
IAPEN
SWBS
SWRST
CMD_FAIL
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SWBS: Software boot selection bit
0: The microcontroller executes the code from user program space (main flash memory) after the software reset. The data
in the user data space remains unchanged.
1: The microcontroller executes the code from ISP space after the software reset. The data in the user data space is
initialized.
SWRST: Software reset trigger bit.
0: No operation
1: Trigger software reset.
Writing 60H to the IAP control register can achieve the effect of cold start of the microcontroller