STC micro STC8A8K64D4 Series - Data Exchange between UART4 and Memory (UR4 T_DMA，UR4 R_DMA); UR4 T_DMA Configuration Register (DMA_UR4 T_CFG); UR4 T_DMA Control Register (DMA_UR4 T_CR); UR4 T_DMA Status Register (DMA_UR4 T_STA)

STC8A8K64D4 Series Manual
- 654 -
23.8 Data exchange between UART4 and memory (UR4T_DMA，
UR4R_DMA)
23.8.1 UR4T_DMA Configuration Register (DMA_UR4T_CFG)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR4T_CFG
FA50H
UR4TIE
-
-
-
UR4TIP[1:0]
UR4TPTY[1:0]
UR4TIE: UR4T_DMA interrupt enable control bit
0: Disable UR4T_DMA interrupt
1: Enable UR4T_DMA interrupt
UR4TIP[1:0]: UR4T_DMA interrupt priority control bits
UR4TIP[1:0]
Interrupt priority
00
Lowest (0)
01
Lower (1)
10
Higher (2)
11
Highest (3)
UR4TPTY[1:0]: UR4T_DMA Data bus access priority control bits
UR4TPTY [1:0]
Bus access priority
00
Lowest (0)
01
Lower (1)
10
Higher (2)
11
Highest (3)
23.8.2 UR4T_DMA Control Register (DMA_UR4T_CR)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR4T_CR
FA51H
ENUR4T
TRIG
-
-
-
-
-
-
ENUR4T: UR4T_DMA function enable control bit
0: Disable UR4T_DMA function
1: Enable UR4T_DMA function
TRIG: UR4T_DMA UART1 transmit trigger control bit
0: Write 0 is invalid
1: Write 1 to start UR4T_DMA automatically sending data.
23.8.3 UR4T_DMA Status Register (DMA_UR4T_STA)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR4T_STA
FA52H
-
-
-
-
-
TXOVW
-
UR4TIF
UR4TIF: UR4T_DMA interrupt request flag bit. When the UR4T_DMA data transmission is completed, the hardware
automatically sets UR4TIF to 1, and if the UR4T_DMA interrupt is enabled, the interrupt service routine is entered.
The flag bit needs to be cleared by software.
TXOVW: UR4T_DMA data coverage flag. When UR4T_DMA is in the process of data transmission, and the UART
writes the SBUF register to trigger the UART to send data again, the data transmission will fail. At this time, the
hardware will automatically set TXOVW to 1. The flag bit needs to be cleared by software.
23.8.4 UR4T_DMA transfer total byte register (DMA_UR4T_AMT)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR4T_AMT
FA53H
DMA_UR4T_AMT: Set the number of bytes of data that needs to be automatically sent.
Note: The actual number of bytes is (DMA_UR4T_AMT+1), that is, when DMA_UR4T_AMT is set to 0, 1
byte is transferred, and when DMA_UR4T_AMT is set to 255, 256 bytes are transferred.