STC micro STC8A8K64D4 Series - Bus Speed Control Register (BUS_SPEED); Bit Addressable Data Memory in 8051

STC8A8K64D4 Series Manual
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7.2.6 Bus speed control register (BUS_SPEED)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
BUS_SPEED
A1H
RW_S[1:0]
SPEED[2:0]
RW_S[1:0]: RD/WR control line selection bit
00: P4.4 is RD, P4.3 is WR
01: P3.7 is RDP3.6 is WR
10: P4.2 is RDP4.0 is WR
11: Reserved.
SPEED[2:0]: Bus read and write speed control (preparation time and hold time of control signal and data signal when reading
and writing data)
instruction
Number of clocks
Access internal expansion RAM
Access external expansion RAM
MOVX A,@Ri
3
3+5* (SPEED+1)
MOVX @Ri,A
3
3+5* (SPEED+1)
MOVX A,@DPTR
2
3+5* (SPEED+1)
MOVX @DPTR,A
2
3+5* (SPEED+1)
The timing of reading and writing external extended RAM is shown in the figure below:
Writing to External Expansion RAM
P2 (A[15:8])
P0 (AD[7:0])
P4.1 (ALE)
P4.4 (RD)
P2 (A[15:8])
P0 (AD[7:0])
P4.1 (ALE)
P4.3 (WR)
High 8-bit address
Lower 8-bit address Data Of being read
High 8-bit address
Lower 8-bit address Data to be written
setup
ADRL
hold
ADRL
setup
DAT
Read
Write
hold
DAT
Read external extended RAM
7.2.7 Bit Addressable Data Memory in 8051
Bit addressable data memory integrated in 8051 single-chip includes two parts: the address range of the first part is 00H ~ 7FH,
and the address range of the second part is 80H ~ FFH. The 00H ~ 7FH bit addressing area is a mapping of the 16 bytes of the data
area 20H ~ 2FH, and the 80H ~ FFh bit addressing area is the 16 special function registers whose addresses are divisible by 8.
(Including 80H, 88H, 90H, 98H, A0H, A8H, B0H, B8H, C0H, C8H, D0H, D8H, E0H, E8H, F0H, F8H).
Address of Data Memory
Address of Bit-addressable
B7
B6
B5
B4
B3
B2
B1
B0
F8H (P7)
FFH
F8H.7
FEH
F8H.6
FDH
F8H.5
FCH
F8H.4
FBH
F8H.3
FAH
F8H.2
F9H
F8H.1
F8H
F8H.0
F0H (B)
F7H
F0H.7
F6H
F0H.6
F5H
F0H.5
F4H
F0H.4
F3H
F0H.3
F2H
F0H.2
F1H
F0H.1
F0H
F0H.0