STC micro STC8A8K64D4 Series - Data Exchange between UART1 and Memory (UR1 T_DMA，UR1 R_DMA); UR1 T_DMA Configuration Register (DMA_UR1 T_CFG); UR1 T_DMA Control Register (DMA_UR1 T_CR); UR1 T_DMA Status Register (DMA_UR1 T_STA)

STC8A8K64D4 Series Manual
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23.5 Data exchange between UART1 and memory (UR1T_DMA，
UR1R_DMA)
23.5.1 UR1T_DMA Configuration Register (DMA_UR1T_CFG)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR1T_CFG
FA30H
UR1TIE
-
-
-
UR1TIP[1:0]
UR1TPTY[1:0]
UR1TIE: UR1T_DMA interrupt enable control bit
0: Disable UR1T_DMA interrupt
1: Enable UR1T_DMA interrupt
UR1TIP[1:0]: UR1T_DMA interrupt priority control bits
UR1TIP[1:0]
Interrupt priority
00
Lowest (0)
01
Lower (1)
10
Higher (2)
11
Highest (3)
UR1TPTY[1:0]: UR1T_DMA Data bus access priority control bits
UR1TPTY [1:0]
Bus access priority
00
Lowest (0)
01
Lower (1)
10
Higher (2)
11
Highest (3)
23.5.2 UR1T_DMA Control Register (DMA_UR1T_CR)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR1T_CR
FA31H
ENUR1T
TRIG
-
-
-
-
-
-
ENUR1T: UR1T_DMA function enable control bit
0: Disable UR1T_DMA function
1: Enable UR1T_DMA function
TRIG: UR1T_DMA UART1 transmit trigger control bit
0: Write 0 is invalid
1: Write 1 to start UR1T_DMA automatically sending data.
23.5.3 UR1T_DMA Status Register (DMA_UR1T_STA)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR1T_STA
FA32H
-
-
-
-
-
TXOVW
-
UR1TIF
UR1TIF: UR1T_DMA interrupt request flag bit. When the UR1T_DMA data transmission is completed, the hardware
automatically sets UR1TIF to 1, and if the UR1T_DMA interrupt is enabled, the interrupt service routine is entered.
The flag bit needs to be cleared by software.
TXOVW: UR1T_DMA data coverage flag. When UR1T_DMA is in the process of data transmission, and the UART
writes the SBUF register to trigger the UART to send data again, the data transmission will fail. At this time, the
hardware will automatically set TXOVW to 1. The flag bit needs to be cleared by software.
23.5.4 UR1T_DMA transfer total byte register (DMA_UR1T_AMT)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
DMA_UR1T_AMT
FA33H
DMA_UR1T_AMT: Set the number of bytes of data that needs to be automatically sent.
Note: The actual number of bytes is (DMA_UR1T_AMT+1), that is, when DMA_UR1T_AMT is set to 0, 1
byte is transferred, and when DMA_UR1T_AMT is set to 255, 256 bytes are transferred.