STC micro STC8A8K64D4 Series - ADC Result Registers (ADC_RES, ADC_RESL); ADC Timing Control Register (ADCTIM)

STC8A8K64D4 Series Manual
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1111
SYSclk/2/16
17.1.3 ADC result registers (ADC_RES, ADC_RESL)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
ADC_RES
BDH
ADC_RESL
BEH
After the A/D conversion is completed, the 10-bit/12-bit conversion result is automatically saved to ADC_RES
and ADC_RESL. Please refer to the RESFMT setting in the ADC_CFG register to see the result's data format.
17.1.4 ADC timing control register (ADCTIM)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
ADCTIM
FEA8H
CSSETUP
CSHOLD[1:0]
SMPDUTY[4:0]
CSSETUP: ADC channel selection time control T
setup
CSSETUP
ADC number of clocks
0
1 (default)
1
2
CSHOLD[1:0]: ADC Channel selection hold time control T
hold
CSHOLD[1:0]
ADC number of clocks
00
1
01
2 (default)
10
3
11
4
SMPDUTY[4:0]: ADC analog signal sampling time control T
duty
(Note: SMPDUTY must not be set less than 01010B)
SMPDUTY[4:0]
ADC number of clocks
00000
1
00001
2
...
...
01010
11 (default)
...
...
11110
31
11111
32
ADC digital-to-analog conversion time: T
convert
The conversion time of 10-bit ADC is fixed at 10 ADC working clocks
The conversion time of 12-bit ADC is fixed at 12 ADC working clocks
A complete ADC conversion time is: Tsetup + Tduty + Thold + Tconvert, as shown in the figure below