STC micro STC8A8K64D4 Series - ADC Configuration Register (ADCCFG)

STC8A8K64D4 Series Manual
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it still needs To enable the ADC channel, you need to set the PxIE register to close the digital input channel
to prevent the external analog input signal from fluctuating high and low and causing additional power
consumption)
ADC_CHS[3:0]
ADC channel
0000
P1.0/ADC0
0001
P1.1/ADC1
0010
P5.4/ADC2
0011
P1.3/ADC3
0100
P1.4/ADC4
0101
P1.5/ADC5
0110
P6.2/ADC6
0111
P6.3/ADC7
1000
P0.0/ADC8
1001
P0.1/ADC9
1010
P0.2/ADC10
1011
P0.3/ADC11
1100
P0.4/ADC12
1101
P0.5/ADC13
1110
P0.6/ADC14
1111
Test internal 1.19V
17.1.2 ADC configuration register (ADCCFG)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
ADCCFG
DEH
-
-
RESFMT
-
SPEED[3:0]
RESFMT: ADC conversion result format control bit
0: The conversion result aligns left. ADC_RES is used to save the upper 8 bits of the result and ADC_RESL is
used to save the lower 4 bits of the result. The format is as follows:
RESFMT=0
ADC_RES ADC_RESL
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D11 D10
0 0 0 0
12 bit conversion result Fill 0 automatically
1: The conversion result aligns right. ADC_RES is used to save the upper 4 bits of the result and ADC_RESL is
used to save the lower 8 bits of the result. The format is as follows:
RESFMT=1
ADC_RES ADC_RESL
D7 D6 D5 D4 D3 D2 D1 D00 0 0 0 D11 D10 D9 D8
12 bit conversion resultFill 0 automatically
SPEED[3:0]: ADC clock control bits {F
ADC
＝SYSclk/2/(SPEED+1)}
SPEED[3:0]
ADC clock frequency
0000
SYSclk/2/1
0001
SYSclk/2/2
0010
SYSclk/2/3
...
...
1101
SYSclk/2/14
1110
SYSclk/2/15