STC8A8K64D4 Series Manual
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11 Interrupt System
(An error will be reported when compiled in Keil when using an interrupt with an interrupt number greater than
31 in a C program. Please refer to Appendix for the solution.)
The interrupt system is set up to give the CPU real-time processing capabilities for external emergencies.
If an emergency request occurrs while CPU is dealing with something, the CPU is required to suspend the current work
to handle the emergency. After the emergency processing is completed, the CPU returns to the place where it was interrupted
and continues the original work. This process is called interrupt. The componet that implements this function is called the
interrupt system. The request source that makes the CPU interrupt to suspend the current work is called the interrupt source.
Microcontroller interrupt system generally allows multiple interrupt sources. When several interrupt sources simultaneously
require the CPU to handle the requests, the CPU should response the interrupt source which has the highest priority. Usually
the CPU handle the interrupt requests according to the priority of interrupt sources. The most urgent incidents have the highest
priority. Each interrupt source has a priority level. The CPU always responds the highest priority interrupt request.
Another interrupt source request with a higher priority takes place while the CPU is processing an interrupt source request,
that is, the CPU is executing the corresponding interrupt service routine, if the CPU can suspend the original interrupt service
routine, and deal with the higher priority interrupt request source, and then return to the original low-level interrupt service
routine after processing finished, this process is called interrupt nesting. Such an interrupt system is called a multi-level
interrupt system, whereas an interrupt system without interrupt nesting is called a single-level interrupt system.
The corresponding interrupt request can be masked by turning off the general enable bit (EA / IE.7) or the corresponding
interrupt enable bit. The CPU can be enabled to respond to the corresponding interrupt request by turning on the corresponding
interrupt enable bit. Every interrupt source can be set or reset independently by software to interrupt enabled or disabled state.
The priority of some interrupts can be set by software. Higher priority interrupt requests can interrupt lower priority interrupts,
whereas lower priority interrupt requests can not interrupt higher priority interrupts. When two interrupts with the same
priority ocuur simultaneously, the inquiry order determines which interrupt the system responds firstly.
11.1 Interrupt sources of STC8A8K64D4 series
The in the following table indicates that the corresponding series have the corresponding interrupt source.
External interrupt 0 (INT0)
Supports falling and edges interrupts
Timer 0 interrrupt (Timer0)
External interrupt 1 (INT1)
Supports falling and edges interrupts
Timer 1 interrrupt (Timer1)
Low voltage detection interrupt (LVD)
CCP/PCA/PWM interrupt (CCP/PCA)
Supports falling, rising and edges interrupts
External interrupt 2 (INT2)
Supports falling edge interrupts
External interrupt 3 (INT3)
Supports falling edge interrupts
Timer 2 interrrupt (Timer2)
External interrupt 4 (INT4)
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