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STC micro STC8A8K64D4 Series - Clock, Reset, Power Saving Mode and Power Management; System Clock Control; System Clock Selection Register (CKSEL); Clock Division Register (CLKDIV)

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STC8A8K64D4 Series Manual
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- 51 -
6. Clock, Reset, Power saving mode and Power
Management
6.1 System Clock Control
The system clock controller provides the clock sources for the microcontroller's CPU and all peripherals. One of the
following three clock sources can be selected as the system clock: internal high-precision IRC, internal 32KHz IRC with large
error, external crystal oscillator. Every clock source can be enabled or disabled respectively using programs, as well as
internally provide clock divider for the purpose of reducing power consumption.
When the microcontroller enters Power-down mode, the clock controller will shut down all clock sources.
internal high-precision IRC
System clock structure diagram
external Crystal oscillator or
external clock
internal 32KHz
MCKSEL[1:0]
00
01
10
11
System clock
(SYSclk)
MCLKODIV[6:0]
CLKDIV[7:0]
P1.6
P5.4
MCLKO_S
0
1
Main Clock
(MCLK)
Related registers
Symbol
Description
Address
Bit Address and Symbol
Reset
value
B7
B6
B5
B4
B3
B2
B1
B0
CKSEL
Clock selection register
FE00H
-
MCKSEL[1:0]
xxxx,xx00
CLKDIV
Clock Division Register
FE01H
nnnn,nnnn
HIRCCR
Internal High speed Oscillator control register
FE02H
ENHIRC
-
-
-
-
-
-
HIRCST
1xxx,xxx0
XOSCCR
External Oscillator control register
FE03H
ENXOSC
XITYPE
XCFILTER[1:0]
GAIN
-
-
XOSCST
00xx,xxx0
IRC32KCR
Internal 32KHz Oscillator control register
FE04H
ENIRC32K
-
-
-
-
-
-
IRC32KST
0xxx,xxx0
MCLKOCR
Main clock output control register
FE05H
MCLKO_S
MCLKODIV[6:0]
0000,0000
IRCDB
Internal IRC start-up and debounce control
FE06H
IRCDB[7:0]
1000,0000
6.1.1 System clock selection register (CKSEL)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
CKSEL
FE00H
-
MCKSEL[1:0]
MCKSEL[1:0]: Main clock source selection
MCKSEL[1:0]
Main clock source
00
internal high speed high precision IRC
01
external high speed crystal oscillator
10
-
11
internal 32KHz low speed IRC
6.1.2 Clock Division register (CLKDIV)
Symbol
Address
B7
B6
B5
B4
B3
B2
B1
B0
CLKDIV
FE01H
CLKDIV: Main clock dividing factor. The system clock (SYSCLK) is the clock signal of main clock (MCLK) after being
divided.
CLKDIV
System clock frequency
0
MCLK/1
1
MCLK/1
2
MCLK/2

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