STC micro STC8A8K64D4 Series - Page 12

STC8A8K64D4 Series Manual
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22.2.1 LCM Interface Configuration Register (LCMIFCFG) ..............................................................628
22.2.2 LCM Interface Configuration Register 2 (LCMIFCFG2) .........................................................629
22.2.3 LCM Interface Control Register (LCMIFCR) ...........................................................................629
22.2.4 LCM Interface Status Register (LCMIFSTA) ...........................................................................629
22.2.5 LCM interface Data Registers (LCMIFDATL, LCMIFDATH) ................................................630
22.3 LCM interface timing diagram ...........................................................................................................631
22.3.1 I8080 mode ................................................................................................................................631
22.3.2 M6800 mode ..............................................................................................................................633
23 DMA 635
23.1 Registers Related to DMA ..................................................................................................................635
23.2 Data read and write between memory and memory (M2M_DMA) ....................................................637
23.2.1 M2M_DMA Configuration Register (DMA_M2M_CFG) ........................................................637
23.2.2 M2M_DMA Control Register (DMA_M2M_CR) ....................................................................637
23.2.3 M2M_DMA Status Register (DMA_M2M_STA) .....................................................................637
23.2.4 M2M_DMA transfer total byte register (DMA_M2M_AMT) ..................................................637
23.2.5 M2M_DMA transfer complete byte register (DMA_M2M_DONE) ........................................638
23.2.6 M2M_DMA Send Address Registers (DMA_M2M_TXAx) ....................................................638
23.2.7 M2M_DMA Receive Address Registers (DMA_M2M_RXAx) ...............................................638
23.3 ADC Automatic Data Storage (ADC_DMA) ......................................................................................639
23.3.1 ADC_DMA Configuration Register (DMA_ADC_CFG) .........................................................639
23.3.2 ADC_DMA Control Register (DMA_ADC_CR) ......................................................................639
23.3.3 ADC_DMA Status Register (DMA_ADC_STA) ......................................................................639
23.3.4 ADC_DMA Receive Address Registers (DMA_ADC_RXAx) .................................................639
23.3.5 ADC_DMA Configuration Register 2 (DMA_ADC_CFG2) ....................................................639
23.3.6 ADC_DMA Channel Enable Registers (DMA_ADC_CHSWx) ...............................................640
23.3.7 Data storage format of ADC_DMA ...........................................................................................641
23.4 Data exchange between SPI and memory (SPI_DMA) ......................................................................642
23.4.1 SPI_DMA Configuration RegisterDMA_SPI_CFG ..........................................................642
23.4.2 SPI_DMA Control Register (DMA_SPI_CR) ...........................................................................643
23.4.3 SPI_DMA Status Register (DMA_SPI_STA) ...........................................................................643
23.4.4 SPI_DMA transfer total byte register (DMA_SPI_AMT) .........................................................644
23.4.5 SPI_DMA transfer complete byte register (DMA_SPI_DONE) ...............................................644
23.4.6 SPI_DMA Send Address Registers (DMA_SPI_TXAx) ...........................................................644
23.4.7 SPI_DMA Receive Address Registers (DMA_SPI_RXAx) ......................................................644
23.4.8 SPI_DMA Configuration Register 2 (DMA_SPI_CFG2) .........................................................644
23.5 Data exchange between UART1 and memory (UR1T_DMAUR1R_DMA) ..................................645
23.5.1 UR1T_DMA Configuration Register (DMA_UR1T_CFG) ......................................................645
23.5.2 UR1T_DMA Control Register (DMA_UR1T_CR) ..................................................................645
23.5.3 UR1T_DMA Status Register (DMA_UR1T_STA) ...................................................................645
23.5.4 UR1T_DMA transfer total byte register (DMA_UR1T_AMT) ................................................645
23.5.5 UR1T_DMA transfer complete byte register (DMA_UR1T_DONE) .......................................646
23.5.6 UR1T_DMA Send Address Registers (DMA_UR1T_TXAx) ..................................................646
23.5.7 UR1R_DMA Configuration Register (DMA_UR1R_CFG) .....................................................646
23.5.8 UR1R_DMA Control Register (DMA_UR1R_CR) ..................................................................646