STC micro STC8A8K64D4 Series - Page 178

STC8A8K64D4 Series Manual
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- 162 -
CCAPM3
PCA3 Mode Control Register
FD54H
-
ECOM3
CCAPP3
CCAPN3
MAT3
TOG3
PWM3
ECCF3
x000,0000
CCAP3L
PCA3 low byte
FD55H
0000,0000
CCAP3H
PCA3 high byte
FD56H
0000,0000
PCA_PWM3
PCA3 󱱕 PWM mode register
FD57H
EBS3[1:0]
XCCAP3H[1:0]
XCCAP3L[1:0]
EPC3H
EPC3L
0000,0000
PINIPL
I/O port interrupt priority low
register
FD60H
P7IP
P6IP
P5IP
P4IP
P3IP
P2IP
P1IP
P0IP
0000,0000
PINIPH
I/O port interrupt priority high
register
FD61H
P7IPH
P6IPH
P5IPH
P4IPH
P3IPH
P2IPH
P1IPH
P0IPH
0000,0000
CHIPID0
Hard ID0
FDE0H
nnnn,nnnn
CHIPID1
Hard ID1
FDE1H
nnnn,nnnn
CHIPID2
Hard ID2
FDE2H
nnnn,nnnn
CHIPID3
Hard ID3
FDE3H
nnnn,nnnn
CHIPID4
Hard ID4
FDE4H
nnnn,nnnn
CHIPID5
Hard ID5
FDE5H
nnnn,nnnn
CHIPID6
Hard ID6
FDE6H
nnnn,nnnn
CHIPID7
Hard ID7
FDE7H
nnnn,nnnn
CHIPID8
Hard ID8
FDE8H
nnnn,nnnn
CHIPID9
Hard ID9
FDE9H
nnnn,nnnn
CHIPID10
Hard ID10
FDEAH
nnnn,nnnn
CHIPID11
Hard ID11
FDEBH
nnnn,nnnn
CHIPID12
Hard ID12
FDECH
nnnn,nnnn
CHIPID13
Hard ID13
FDEDH
nnnn,nnnn
CHIPID14
Hard ID14
FDEEH
nnnn,nnnn
CHIPID15
Hard ID15
FDEFH
nnnn,nnnn
CHIPID16
Hard ID16
FDF0H
nnnn,nnnn
CHIPID17
Hard ID17
FDF1H
nnnn,nnnn
CHIPID18
Hard ID18
FDF2H
nnnn,nnnn
CHIPID19
Hard ID19
FDF3H
nnnn,nnnn
CHIPID20
Hard ID20
FDF4H
nnnn,nnnn
CHIPID21
Hard ID21
FDF5H
nnnn,nnnn
CHIPID22
Hard ID22
FDF6H
nnnn,nnnn
CHIPID23
Hard ID23
FDF7H
nnnn,nnnn
CHIPID24
Hard ID24
FDF8H
nnnn,nnnn
CHIPID25
Hard ID25
FDF9H
nnnn,nnnn
CHIPID26
Hard ID26
FDFAH
nnnn,nnnn
CHIPID27
Hard ID27
FDFBH
nnnn,nnnn
CHIPID28
Hard ID28
FDFCH
nnnn,nnnn
CHIPID29
Hard ID29
FDFDH
nnnn,nnnn
CHIPID30
Hard ID30
FDFEH
nnnn,nnnn
CHIPID31
Hard ID31
FDFFH
nnnn,nnnn
DMA_M2M_CR
M2M_DMA control register
FA01H
ENM2M
TRIG
-
-
-
-
-
-
00xx,xxxx
DMA_M2M_STA
M2M_DMA status register
FA02H
-
-
-
-
-
-
-
M2MIF
xxxx,xxx0
DMA_M2M_AMT
M2M_DMA total bytes to be
transferred
FA03H
0000,0000
DMA_M2M_DONE
M2M_DMA transfer completed bytes
FA04H
0000,0000
DMA_M2M_TXAH
M2M_DMA send address high byte
FA05H
0000,0000
DMA_M2M_TXAL
M2M_DMA send address low byte
FA06H
0000,0000
DMA_M2M_RXAH
M2M_DMA receive address high
byte
FA07H
0000,0000
DMA_M2M_RXAL
M2M_DMA receive address low byte
FA08H
0000,0000
DMA_ADC_CFG
ADC_DMA configuration register
FA10H
ADCIE
-
-
-
ADCMIP[1:0]
ADCPTY[1:0]
0xxx,0000
DMA_ADC_CR
ADC_DMA control register
FA11H
ENADC
TRIG
-
-
-
-
-
-
00xx,xxxx
DMA_ADC_STA
ADC_DMA status register
FA12H
-
-
-
-
-
-
-
ADCIF
xxxx,xxx0
DMA_ADC_RXAH
ADC_DMA receive address high
byte
FA17H
0000,0000
DMA_ADC_RXAL
ADC_DMA receive address low byte
FA18H
0000,0000
DMA_ADC_CFG2
ADC_DMA configuration register 2
FA19H
-
-
-
-
CVTIMESEL[3:0]
xxxx,0000
DMA_ADC_CHSW0
ADC_DMA channel enable 0
FA1AH
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
1000,0000
DMA_ADC_CHSW1
ADC_DMA channel enable 1
FA1BH
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
0000,0001
DMA_SPI_CFG
SPI_DMA configuration register
FA20H
SPIIE
ACT_TX
ACT_RX
-
SPIIP[1:0]
SPIPTY[1:0]
000x,0000
DMA_SPI_CR
SPI_DMA control register
FA21H
ENSPI
TRIG_M
TRIG_S
-
-
-
-
CLRFIFO
000x,xxx0
DMA_SPI_STA
SPI_DMA status register
FA22H
-
-
-
-
-
TXOVW
RXLOSS
SPIIF
xxxx,x000
DMA_SPI_AMT
SPI_DMA total bytes to be
transferred
FA23H
0000,0000
DMA_SPI_DONE
SPI_DMA transfer completed bytes
FA24H
0000,0000
DMA_SPI_TXAH
SPI_DMA send address high byte
FA25H
0000,0000
DMA_SPI_TXAL
SPI_DMA send address low byte
FA26H
0000,0000
DMA_SPI_RXAH
SPI_DMA receive address high byte
FA27H
0000,0000
DMA_SPI_RXAL
SPI_DMA receive address low byte
FA28H
0000,0000
DMA_SPI_CFG2
SPI_DMA configuration register 2
FA29H
-
-
-
-
-
WRPSS
SSS[1:0]
xxxx,x000
DMA_UR1T_CFG
UR1T_DMA configuration register
FA30H
UR1TIE
-
-
-
UR1TIP[1:0]
UR1TPTY[1:0]
0xxx,0000
DMA_UR1T_CR
UR1T_DMA control register
FA31H
ENUR1T
TRIG
-
-
-
-
-
-
00xx,xxxx
DMA_UR1T_STA
UR1T_DMA status register
FA32H
-
-
-
-
-
TXOVW
-
UR1TIF
xxxx,x0x0
DMA_UR1T_AMT
UR1T_DMA total bytes to be
transferred
FA33H
0000,0000
DMA_UR1T_DONE
UR1T_DMA transfer completed
bytes
FA34H
0000,0000
DMA_UR1T_TXAH
UR1T_DMA send address high byte
FA35H
0000,0000
DMA_UR1T_TXAL
UR1T_DMA send address low byte
FA36H
0000,0000
DMA_UR1R_CFG
UR1R_DMA configuration register
FA38H
UR1RIE
-
-
-
UR1RIP[1:0]
UR1RPTY[1:0]
0xxx,0000
DMA_UR1R_CR
UR1R_DMA control register
FA39H
ENUR1R
-
TRIG
-
-
-
-
CLRFIFO
0x0x,xxx0