STC8A8K64D4 Series Manual
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✓ Online debugging with single chip is supported, and no dedicated emulator is needed. The number of breakpoints is unlimited
theoratically.
➢ SRAM
✓ 128 bytes internal direct access RAM (DATA, use keyword data to declare in C language program)
✓ 128 bytes internal indirect access RAM (IDATA, use keyword idata to declare in C language program)
✓ 8192 bytes internal extended RAM (internal XDATA, use keyword xdata to declare in C language program)
➢ Clock
✓ Internal high precise RC clock(IRC for short, ranges from 4MHz to 45MHz), adjustable while ISP and can be divided to lower
frequency by user software, 100KHz for instance.
✓ Error:0.3% (at the temperature 25)
✓ -1.38%+1.42% temperature drift (at the temperature range of -40°C to +85°C)
✓ -0.88%+1.05% temperature drift (at the temperature range of -20 to 65)
✓ Internal 32KHz low speed IRC with large error
✓ External 4MHz~45MHz oscillator or external clock
➢ Reset
✓ Hardware reset
✓ Power-on reset. Measured voltage value is 1.69V~1.82V.
(Effective when the chip does not enable the low voltage reset function)
The power-on reset voltage is a voltage range consisting of an upper limit voltage and a lower limit voltage. When the
operating voltage drops from 5V / 3.3V to the lower limit threshold voltage of the power-on reset, the chip is in reset state.
When the voltage rises from 0V to the upper threshold voltage of power-on reset, the chip is released from the reset state.
✓ Reset by reset pin. The default function of P5.4 is the I/O port. P5.4 pin can be set as the reset pin while ISP download.
(Note: When the P5.4 pin is set as the reset pin, the reset level is low.)
✓ Watch dog timer reset
✓ Low voltage detection reset. 4 low voltage detection levels are provided, 2.0V (Measured as 1.90V~2.04V), 2.4V
(Measured as 2.30V~2.50V), 2.7V(Measured as 2.61V~2.82V), 3.0V(Measured as 2.90V~3.13V).
Each level of low-voltage detection voltage is a voltage range consisting of an upper limit voltage and a lower limit voltage.
When the operating voltage drops from 5V / 3.3V to the lower limit threshold voltage of low-voltage detection, the low-
voltage detection takes effect. When the voltage rises from 0V to the upper threshold voltage, the low voltage detection
becomes effective.
✓ Software reset
✓ Writing the reset trigger register using software
➢ Interrupts
✓ 43 interrupt sources: INT0(Supports rising edge and falling edge interrupt), INT1(Supports rising edge and falling edge
interrupt), INT2(Supports falling edge interrupt only), INT3(Supports falling edge interrupt only), INT4(Supports falling edge
interrupt only), timer 0, timer 1, timer 2, timer 3, timer 4, UART 1, UART 2, UART 3, UART 4, ADC, LVD, SPI, I
2
C, comparator,
PCA/CCP/PWM, Enhanced PWM, Enhanced PWM Anomaly Detection, all I/O interrupts (8 groups), LCD driver, DMA receive
and transmit interrupts of USART 1, DMA receive and transmit interrupts of USART 2, DMA receive and transmit interrupts of
UART 3, DMA receive and transmit interrupts of UART 4, DMA interrupt of SPI, DMA interrupt of ADC, DMA interrupt of
LCD driver and DMA interrupt of memory-to-memory.
✓ 4 interrupt priority levels
✓ Interrupts that can wake up the CPU in clock stop mode: INT0(P3.2), INT1(P3.3), INT2(P3.6), INT3(P3.7), INT4(P3.0),
T0(P3.4), T1(P3.5), T2(P1.2), T3(P0.4), T4(P0.6), RXD(P3.0/P3.6/P1.6/P4.3), RXD2(P1.0/P4.0), RXD3(P0.0/P5.0),
RXD4(P0.2/P5.0), CCP0(P1.7/P2.3/P7.0/P3.3), CCP1(P1.6/P2.4/P7.1/P3.2), CCP2(P1.5/P2.5/P7.2/P3.1),
CCP3(P1.4/P2.6/P7.3/P3.0), I2C_SDA(P1.4/P2.4/P3.3), SPI_SS(P1.2/P2.2/P3.5), all I/O interrupts, Comparator interrupt, LVD
interrupt, Power-down wake-up timer.
➢ Digital peripherals
✓ 5 16-bit timers: timer0, timer1, timer2, timer 3, timer 4, where the mode 3 of timer 0 has the Non-Maskable Interrupt (NMI in
short) function. Mode 0 of timer 0 and timer 1 is 16-bit Auto-reload mode.
✓ 4 high speed UARTs: UART1, UART2, UART3, UART4, whose maximum baudrate clock may be FOSC/4
✓ 4 groups of 16-bit PCA modules: CCP0, CCP1, CCP2, CCP3, which can be used for capture, high-speed pulse output, and
6/7/8/10-bit PWM output
✓ 8 groups of 15-bit enhanced PWMs, which can realize control signals with dead time, and support external fault detection
function. In addition, there are 4 groups of traditional PCA/CCP/PWM can be used as PWM.
✓ SPI: Master mode, slave mode or master/slave automatic switch mode are supported.
✓ I
2
C: Master mode or slave mode are supported.
✓ MDU16: Hardware 16-bit Multiplier and Divider which supports operations such as 32-bit divided by 16-bit, 16-bit divided by
16-bit, 16-bit multiplied by 16-bit, data shift, and data normalization.
✓ I/O port interrupt: All I/Os support interrupts, each group of I/O interrupts has an independent interrupt entry address, all I/O
interrupts can support 4 types interrupt mode: high level interrupt, low level interrupt, rising edge interrupt, falling edge interrupt.
Provides 4 levels of interrupt priority and supports power-down wake-up function.
(The I/O port interrupts of this series can wake up CPU from power-down, and have 4 levels of interrupt priority)
✓ LCD dirver: support 8080 and 6800 interface, and support 8-bit and 16-bit data width.
✓ DMA: Support SPI shift to receive data to memory, SPI shift to send data from memory, I2C receive data to memory, USART
1/2/3/4 receive data to memory, USART 1/2/3/4 send data from memory, ADC automatically sample data to memory (calculate
average value at the same time), LCD driver send data from memory, and copy data from memory to memory
✓ Hardware digital ID: support 32 bytes
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