STC micro STC8A8K64D4 Series - Page 6

STC8A8K64D4 Series Manual
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11.5.13 UART1 Interrupt ......................................................................................................................242
11.5.14 UART2 Interrupt ......................................................................................................................244
11.5.15 UART3 Interrupt ......................................................................................................................246
11.5.16 UART4 Interrupt ......................................................................................................................249
11.5.17 LVD Interrupt ..........................................................................................................................251
11.5.18 SPI Interrupt ............................................................................................................................253
11.5.19 Comparator Interrupt ...............................................................................................................255
11.5.21 I2C Interrupt ............................................................................................................................257
12 I/O port interrupt .......................................................................................................................................260
12.1 I/O port interrupt related registers .......................................................................................................260
12.1.1 Port interrupt enable registers (PxINTE) ...................................................................................261
12.1.2 Port interrupt flag registers (PxINTF) .......................................................................................261
12.1.3 Port interrupt mode configuration registers (PxIM0PxIM1) .................................................262
12.1.4 Port interrupt priority control registers (PINIPL, PINIPH) .......................................................262
12.1.5 Port interrupt power-down wake-up enable registers (PxWKUE) ............................................262
12.2 Example Routines ...............................................................................................................................264
12.2.1 P0 Falling edge interrupt ...........................................................................................................264
12.2.2 P1 rising edge interrupt ..............................................................................................................268
12.2.3 P2 low level interrupt ................................................................................................................272
12.2.4 Port3 high level interrupt ...........................................................................................................275
13 Timer/Counter ............................................................................................................................................280
13.1 Registers Related to Timers ................................................................................................................280
13.2 Timer 0/1.............................................................................................................................................281
13.2.1 Timer 0 and 1 Control Register .................................................................................................281
13.2.2 Timer 0/1 Mode Register ...........................................................................................................281
13.2.3 Timer0 mode 0 (16-bit auto-reloadable mode) ......................................................................282
13.2.4 Timer0 mode 1 (16-bit non-autoreloadable mode) ...............................................................283
13.2.5 Timer 0 mode 2 (8-bit auto-reloadable mode) .......................................................................284
13.2.6 Timer 0 mode 3 (16-bit auto-realoadable mode with non-maskable interrupt, which can be
used as real-time operating system metronome) ..............................................................................284
13.2.7 Timer 1 mode 0 (16-bit auto-reloadable mode) .....................................................................285
13.2.8 Timer1 mode 1 (16-bit non-autoreloadable mode) ...............................................................286
13.2.9 Timer 1 mode 2 (8-bit auto-reloadable mode) .......................................................................287
13.2.10 Timer 0 Counting Registers .....................................................................................................287
13.2.11 Timer 1 Counting Registers .....................................................................................................287
13.2.12 Auxiliary Register 1 (AUXR) ..................................................................................................288
13.2.13 External Interrupt and Clock Output Control Register (INTCLKO) .......................................288
13.2.14 Timer 0 calculation formula ....................................................................................................288
13.2.15 Timer 1 calculation formula ....................................................................................................288
13.3 Timer 2 (24-bit timer, 8-bit prescaler + 16-bit timing)........................................................................290
13.3.1 Auxiliary Register 1 (AUXR) ....................................................................................................290
13.3.2 External Interrupt and Clock Output Control Register (INTCLKO) .........................................290
13.3.3 Timer 2 Counting Registers .......................................................................................................290
13.3.4 Timer 2 8-bit Prescaler Register (TM2PS) ................................................................................290