STC micro STC8A8K64D4 Series - Page 679

STC8A8K64D4 Series Manual
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DMA_UR1T_STA &= ~0x01;
DMATxFlag = 1;
}
if (DMA_UR1T_STA & 0x04) //data coverage
{
DMA_UR1T_STA &= ~0x04;
}
if (DMA_UR1R_STA & 0x01) //Receive complete
{
DMA_UR1R_STA &= ~0x01;
DMARxFlag = 1;
}
if (DMA_UR1R_STA & 0x02) //data is discarded
{
DMA_UR1R_STA &= ~0x02;
}
}
//File: ISR.ASM
//Interrupts with interrupt numbers greater than 31 require interrupt entry address remapping processing
CSEG AT 012BH ;P0INT_VECTOR
JMP P0INT_ISR
CSEG AT 0133H ;P1INT_VECTOR
JMP P1INT_ISR
CSEG AT 013BH ;P2INT_VECTOR
JMP P2INT_ISR
CSEG AT 0143H ;P3INT_VECTOR
JMP P3INT_ISR
CSEG AT 014BH ;P4INT_VECTOR
JMP P4INT_ISR
CSEG AT 0153H ;P5INT_VECTOR
JMP P5INT_ISR
CSEG AT 015BH ;P6INT_VECTOR
JMP P6INT_ISR
CSEG AT 0163H ;P7INT_VECTOR
JMP P7INT_ISR
CSEG AT 016BH ;P8INT_VECTOR
JMP P8INT_ISR
CSEG AT 0173H ;P9INT_VECTOR
JMP P9INT_ISR
CSEG AT 017BH ;M2MDMA_VECTOR
JMP M2MDMA_ISR
CSEG AT 0183H ;ADCDMA_VECTOR
JMP ADCDMA_ISR
CSEG AT 018BH ;SPIDMA_VECTOR
JMP SPIDMA_ISR
CSEG AT 0193H ;U1TXDMA_VECTOR
JMP U1TXDMA_ISR
CSEG AT 019BH ;U1RXDMA_VECTOR
JMP U1RXDMA_ISR
CSEG AT 01A3H ;U2TXDMA_VECTOR
JMP U2TXDMA_ISR
CSEG AT 01ABH ;U2RXDMA_VECTOR
JMP U2RXDMA_ISR
CSEG AT 01B3H ;U3TXDMA_VECTOR
JMP U3TXDMA_ISR