Appendix U Precautions for STC8A8K64D4 series
MCU to replace STC8A8K64S4A12 series
◼ I/O port
After the STC8A8K64D4 series MCU is powered on, the I/O mode is different from that of the
STC8A8K64S4A12 series. All I/O ports of STC8A8K64S4A12 series single-chip microcomputers are in 8051 quasi-
bidirectional port mode after power-on. In the I/O of STC8A8K64D4 series single-chip microcomputers, except for
ISP download pins P3.0/P3.1 which are quasi-bidirectional port modes, all the other I/O ports are in high-impedance
input mode after power on. All I/O ports of the traditional 8051 are in quasi-bidirectional port mode and output high
level after power-on. Often customers use I/O to drive motors or LED lights in their systems, so there will be moments
when the single-chip microcomputer is powered on. Move it once or the LED will flash once. The I/O of the
STC8A8K64D4 series is in high-impedance input mode after power-on, which can avoid this kind of malfunction of
the motor and LED.
Except ISP download pin P3.0/P3.1 which is quasi-bidirectional port mode, all other I/O ports of STC8A8K64D4
series are in high-impedance input mode after power-on, so the two registers PxM0 and PxM1 must be used to set the
I/O working mode before the I/O ports output signals.
◼ Reset foot
The P5.4 port of the STC8A8K64D4 series and STC8A8K64S4A12 series is generally used as a normal I/O port.
When the user sets P5.4 as the reset pin function during ISP download, the P5.4 port is the reset of the microcontroller
Pin (RESET pin). For the STC8A8K64S4A12 series, when the reset pin is high, the microcontroller is in the reset state,
and when the reset pin is low, the microcontroller is released from the reset state. The reset levels of STC8A8K64D4
series and STC8A8K64S4A12 series are reversed, that is, for STC8A8K64D4 series, when the reset pin is low, the
microcontroller is in the reset state, and when the reset pin is high, the microcontroller is released from the reset state.
Therefore, when the user enables the reset pin function of port P5.4, it is necessary to pay attention to the reset
level.
◼ EEPROM
The waiting time for EEPROM erasing and programming of STC8A8K64S4A12 series is set by Bit2-Bit0 of the
register IAP_CONTR. The setting is only an approximate frequency range value. The STC8A8K64D4 series adds a
new register IAP_TPS (SFR address: 0F5H), dedicated to setting EEPROM erasing In addition to the waiting time for
programming, and the user does not need to calculate, just fill in IAP_TPS directly according to the current CPU
working frequency, and the hardware will automatically calculate the waiting time. (For example: the current CPU
operating frequency is 24MHz, you only need to fill in 24 to IAP_TPS).
◼ ADC
The ADCs of the STC8A8K64D4 series are fully functionally compatible with the STC8A8K64S4A12 series.
Based on the STC8A8K64S4A12 series ADC, the STC8A8K64D4 series adds new functions such as external trigger
function and automatic multiple conversion and averaging.
◼ Comparators
The positive input of the STC8A8K64D4 series comparator is 4-way optional, and the negative input is two-
way optional. The input selection is set in the register CMPEXCFG. The STC8A8K64S4A12 series are
inconsistent.
◼ SPI
The 4 SPI clock frequencies of the STC8A8K64D4 series are: SYSclk/4, SYSclk/8, SYSclk/16 and
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