Advanced-control timers (TIM1/TIM8/TIM20) RM0440
1098/2126 RM0440 Rev 4
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The repetition counter is reloaded with the content of TIMx_RCR register.
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 278. Counter timing diagram, internal clock divided by 1
MSv62305V1
36
34
33
32 31
30 2F
04
03
02 01 00
05
tim_psc_ck
CEN
tim_cnt_ck
Counter register
Update event (UEV)
Counter underflow
(cnt_udf)
Update interrupt flag
(UIF)
35
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