ST STM32G473

Flexible static memory controller (FSMC) RM0440
544/2126 RM0440 Rev 4
The FMC supports both NOR Flash wait state configurations, for each chip select, thanks to
the WAITCFG bit in the FMC_BCRx registers (x = 0..3).
Figure 69. Wait configuration waveforms
addr[15:0] data data
addr[25:16]
Memory transaction = burst of 4 half words
HCLK
CLK
A[25:16]
NADV
NWAIT
(WAITCFG = 1)
A/D[15:0]
inserted wait state
data
NWAIT
(WAITCFG = 0)
ai15798c