RM0440 Rev 4 1139/2126
RM0440 Advanced-control timers (TIM1/TIM8/TIM20)
1226
be used in Output compare and PWM modes. It does not work in Forced mode.
tim_ocref_clr_int input can be selected between the tim_ocref_clr input and tim_etrf
(tim_etr_in after the filter) by configuring the OCCS bit in the TIMx_SMCR register.
The tim_ocref_clr input can be selected among several inputs, using the
OCRSEL[2:0] bitfield in the TIMx_AF2 register, as shown on the Figure 321 below. Refer to
Section 28.3.2: TIM1/TIM8/TIM20 pins and internal signals for a list of sources available in
the product.
Figure 321. tim_ocref_clr input selection multiplexer
When tim_etrf is chosen, tim_etr_in must be configured as follows:
1. The External Trigger Prescaler must be kept off: bits ETPS[1:0] of the TIMx_SMCR
register set to ‘00’.
2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
‘0’.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to application needs (as per polarity of the source connected to
the trigger and eventual need to remove noise using the filter).
Figure 322 shows the behavior of the tim_ocxref signal when the tim_etrf Input becomes
High, for both values of the enable bit OCxCE. In this example, the timer TIMx is
programmed in PWM mode.
MSv62341V1
OCRSEL[2:0] OCCS
tim_ocref_clr
TIMx_AF2
tim_ocref_clr8
tim_ocref_clr1
tim_ocref_clr2
tim_ocref_clr3
tim_ocref_clr4
tim_ocref_clr5
tim_ocref_clr6
tim_ocref_clr7
tim_etrf
tim_ocref_clr_int
TIMx_SMCR
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