Advanced-control timers (TIM1/TIM8/TIM20) RM0440
1118/2126 RM0440 Rev 4
PWM edge-aligned mode
• Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the
Upcounting mode on page 1093.
In the following example, we consider PWM mode 1. The reference PWM signal
tim_ocxref is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then tim_ocxref is held at ‘1’. If the compare value is 0 then tim_ocxref is held at ‘0’.
Figure 302 shows some edge-aligned PWM waveforms in an example where
TIMx_ARR=8.
Figure 302. Edge-aligned PWM waveforms (ARR=8)
• Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the
Downcounting mode on page 1097
In PWM mode 1, the reference signal tim_ocxref is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then tim_ocxref is held at ‘1’. 0%
PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the tim_ocxref/tim_ocx
signals). The compare flag is set when the counter counts up, when it counts down or both
when it counts up and down depending on the CMS bits configuration. The direction bit
MSv62327V1
Counter register
‘1’
0
12 3456 7801
tim_ocxref
CCxIF
tim_ocxref
CCxIF
tim_ocxref
CCxIF
tim_ocxref
CCxIF
CCRx=4
CCRx=8
CCRx>8
CCRx=0
‘0’
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