RM0440 Rev 4 2045/2126
RM0440 USB Type-C™ / USB Power Delivery interface (UCPD)
2079
The following table lists key internal signals.
46.4.2 UCPD reset and clocks
The peripheral has a single reset signal (APB bus reset).
The register section is clocked with the APB clock (ucpd_pclk).
The main functional part of the transmitter is clocked with ucpd_clk clock, pre-scaled from
the ucpd_ker_ck (HSI16) clock according to the PSC_USBPDCLK[2:0] bitfield of the
UCPD_CFGR1 register. The main functional part of the receiver is clocked with the
ucpd_rx_clk recovered from the incoming bitstream.
The receiver is designed to work in the clock frequency range from 6 to 18 MHz. However,
the optimum performance is ensured in the range from 9 to 18 MHz.
The following diagram shows the clocking and timing elements of the UCPD peripheral.
Figure 674. Clock division and timing elements
Refer to the USB PD specification in order to set appropriate delays. For tTransitionWindow
and especially for tInterFrameGap, the clock frequency uncertainty must be taken into
account so as to respect specified timings in all cases.
Table 420. UCPD internal signals
Internal signal name Signal type Description
ucpd_pclk Input APB clock for registers
ucpd_ker_ck Input Kernel clock
ucpd_tx_dma Input/Output Rx DMA acknowledge / request
ucpd_rx_dma Input/Output Tx DMA acknowledge / request
ucpd_it Output Interrupt request (all interrupts OR-ed) connected to NVIC
ucpd_wkup Output Wakeup request connected to EXTI
clk_rq Output Clock request connected to RCC
MSv45536V2
Counters
Clock division
Pre-scaler
/1 to /16
“Half bit” divider
/1 to /64
“tTransitionWindow”
2 to 32
“tInterFrameGap”
2 to 32
BMC transmitter
BMC receiver
ucpd_ker_ck
hbit_clk (~ 600 kHz)
ucpd_pclk
Registers
PSC_USBPDCLK[2:0]
HBITCLKDIV[5:0]
TRANSWIN[4:0]
ucpd_clk
IFRGAP[4:0]
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