RM0440 Rev 4 1637/2126
RM0440 Universal synchronous/asynchronous receiver transmitter (USART/UART)
1733
RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and
CTSE bits to ‘1’ in the USART_CR3 register.
RS232 RTS flow control
If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the
USART receiver is ready to receive a new data. When the receive register is full, nRTS is
deasserted, indicating that the transmission is expected to stop at the end of the current
frame. Figure 553 shows an example of communication with RTS flow control enabled.
Figure 553. RS232 RTS flow control
Note: When FIFO mode is enabled, nRTS is deasserted only when RXFIFO is full.
RS232 CTS flow control
If the CTS flow control is enabled (CTSE=1), then the transmitter checks the nCTS input
before transmitting the next frame. If nCTS is asserted (tied low), then the next data is
transmitted (assuming that data is to be transmitted, in other words, if TXE/TXFE=0), else
the transmission does not occur. When nCTS is deasserted during a transmission, the
current transmission is completed before the transmitter stops.
When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the nCTS
input toggles. It indicates when the receiver becomes ready or not ready for communication.
An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. Figure 554
shows an example of communication with CTS flow control enabled.
MSv31168V2
Start
bit
Start
bit
Stop
bit
Idle
Stop
bit
RX
RTS
Data 1 read
Data 2 can now be transmitted
RXNE
RXNE
Data 1 Data 2
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