RM0440 Rev 4 1869/2126
RM0440 Inter-integrated circuit (I2C) interface
1928
41.4.7 Data transfer
The data transfer is managed through transmit and receive data registers and a shift
register.
Reception
The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is
received), the shift register is copied into I2C_RXDR register if it is empty (RXNE=0). If
RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line
is stretched low until I2C_RXDR is read. The stretch is inserted between the 8th and 9th
SCL pulse (before the Acknowledge pulse).
Figure 633. Data reception
xx
Shift register
data1
data1
xx data2
RXNE
ACK pulse
data0 data2
ACK pulse
xx
I2C_RXDR
rd data1rd data0
SCL
legend:
SCL
stretch
MS19848V1
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