Digital-to-analog converter (DAC) RM0440
742/2126 RM0440 Rev 4
The STRSTTRIG signal has higher priority than STINCTRIG. Thetrigger signal cannot be
faster than the DAC_DORx update rate defined in the Table 187: HFSEL description. If
STINCTRIG is asserted faster than the allowed data update rate, the STINCTRIG trigger is
ignored. If the STRSTTRIG signal is applied after the STINCTRIG and before DAC_DORx
update rate constraints, STRSTTRIG is put on hold. Then, immediately after the data
increment, the reset trigger is applied.
Figure 166. DAC sawtooth STINCTRIG and STRSTTRIG priority (STDIR = 0)
22.4.12 DAC channel modes
Each DAC channel can be configured in Normal mode or Sample and hold mode. The
output buffer can be enabled to allow a high drive capability. Before enabling output buffer,
the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded
after reset) and can be adjusted by software during application operation.
Normal mode
In Normal mode, there are four combinations, by changing the buffer state and by changing
the DAC_OUTx pin interconnections.
To enable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:
• 000: DAC is connected to the external pin
• 001: DAC is connected to external pin and to on-chip peripherals
To disable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:
• 010: DAC is connected to the external pin
• 011: DAC is connected to on-chip peripherals
MSv46132V1
0
STRSTDATA[11:0]
Vlaue
STRSTTRIG signal
STINCTRIG signal
MAX data rate
(or update delay)
ignored
update
update
not ignored
update
reset
ignored
update
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