Embedded Flash memory (FLASH) for category 2 devices RM0440
188/2126 RM0440 Rev 4
5 Embedded Flash memory (FLASH)
for category 2 devices
5.1 Introduction
The Flash memory interface manages CPU AHB ICode and DCode accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
5.2 FLASH main features
• Up to 128 Kbyte of Flash memory (single bank).
• Flash memory read operations with 64 bits data width
• Page erase and mass erase
Flash memory interface features:
• Flash memory read operations
• Flash memory program/erase operations
• Read protection activated by option (RDP)
• 2 Write protection areas selected by option
• Proprietary code read protection areas defined by option
• Securable memory areas defined by option
• Prefetch on ICODE
• Instruction Cache: 32 cache lines of 4 x 64 bits on ICode (1 KB RAM)
• Data Cache: 8 cache lines of 4 x 64 bits on DCode (256B RAM)
• Error Code Correction ECC: 8 bits per 64-bit double-word
– 8 + 64 = 72 bits, 2 bits detection, 1 bit correction
• Option byte loader
• Low-power mode
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