ST STM32G473 - Figure 285. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0 X36; Figure 286. Counter Timing Diagram, Internal Clock Divided by N

RM0440 Rev 4 1103/2126
RM0440 Advanced-control timers (TIM1/TIM8/TIM20)
1226
Figure 285. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
Figure 286. Counter timing diagram, internal clock divided by N
MSv62312V1
0034 0035
tim_psc_ck
tim_cnt_ck
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
CEN
Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow
0036 0035
MSv62313V1
00
1F
20
tim_psc_ck
tim_cnt_ck
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
01