Digital-to-analog converter (DAC) RM0440
734/2126 RM0440 Rev 4
22.4.3 DAC channel enable
Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR
register. The DAC channel is then enabled after a t
WAKEUP
startup time.
DACxRDY bit is set in the DAC_SR register when the DAC interface is ready to accept data.
Writing new data or asserting the trigger is not allowed when ENx bit is set while DACxRDY
signal is reset.
Note: The ENx bit enables the analog DAC channelx only. The DAC channelx digital interface is
enabled even if the ENx bit is reset.
22.4.4 DAC data format
Depending on the selected configuration mode, the data have to be written into the specified
register as described below:
• Single DAC channel
There are three possibilities:
– 8-bit right alignment: the software has to load data into the DAC_DHR8Rx[7:0] bits
(stored into the DHRx[11:4] bits)
– 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4]
bits (stored into the DHRx[11:0] bits)
– 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0]
bits (stored into the DHRx[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHRx (data holding registerx, which are internal non-memory-
mapped registers). The DHRx register is then loaded into the DORx register either
automatically, by software trigger or by an external event trigger.
Figure 157. Data registers in single DAC channel mode
dac_inc_chx_trg13 (x = 1, 2) hrtim_dac_step_trg5
Internal signal from on-chip
timers
dac_inc_chx_trg14 (x = 1, 2) hrtim_dac_step_trg6
Internal signal from on-chip
timers
Table 185. DAC4 interconnection (continued)
Signal name Source Source type
31 24 15 7 0
8-bit right aligned
12-bit left aligned
12-bit right aligned
ai14710b
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