ST STM32G473 User Manual

Reset and clock control (RCC) RM0440
274/2126 RM0440 Rev 4
1. Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in
User option Bytes. In this case, whenever a Standby mode entry sequence is
successfully executed, the device is reset instead of entering Standby mode.
2. Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in User
option bytes. In this case, whenever a Stop mode entry sequence is successfully
executed, the device is reset instead of entering Stop mode.
3. Entering Shutdown mode: this type of reset is enabled by resetting nRST_SHDW bit in
User option bytes. In this case, whenever a Shutdown mode entry sequence is
successfully executed, the device is reset instead of entering Shutdown mode.
For further information on the User Option Bytes, refer to Section 3.4.1: Option bytes
description.
Option byte loader reset
The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.
7.1.3 RTC domain reset
The RTC domain has two specific resets.
A RTC domain reset is generated when one of the following events occurs:
1. Software reset, triggered by setting the BDRST bit in the RTC domain control register
(RCC_BDCR).
2. V
DD
or V
BAT
power on, if both supplies have previously been powered off.
A RTC domain reset only affects the LSE oscillator, the RTC, the Backup registers and the
RCC RTC domain control register.
7.2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
• HSI16 (high speed internal)16 MHz RC oscillator clock
• HSE oscillator clock, from 4 to 48 MHz
• PLL clock
The HSI16 is used as system clock source after startup from Reset.
The devices have the following additional clock sources:
• 32 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop and Standby modes.
• 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK).
• RC 48 MHz internal clock sources (HSI48) to potentially drive the USB FS and the
RNG.
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Several prescalers can be used to configure the AHB frequency, the APB1 and APB2
domains. The maximum frequency of the AHB, the APB1 and the APB2 domains is
170 MHz.

ST STM32G473 Specifications

General

Brand	ST
Model	STM32G473
Category	Microcontrollers
Language	English