RM0440 Rev 4 1243/2126
RM0440 General-purpose timers (TIM2/TIM3/TIM4/TIM5)
1343
Figure 370. Counter timing diagram, internal clock divided by N
Figure 371. Counter timing diagram, Update event
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-
MSv62308V1
001F20
tim_psc_ck
tim_cnt_ck
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
36
MSv62309V1
FF 36
tim_pasc_ck
tim_cnt_ck
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
0002030405 30 2F3233343536 3101
CEN
Auto-reload preload
register
Write a new value in TIMx_ARR
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